Abstract
Memory chips are always at the leading edge of integration and their size gives permanently the state of the art of the technology. As the design is very repetitive, no other factor such as architecture choices or innovative layout is very decisive. The state of the art has led to 1 Mbit static RAMs in CMOS technology (0.8 µm) with 25 ns access time. This state of the art is summarized in table I in appendix 1.
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© 1989 Plenum Press, New York
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Nasreddine, B., Kouka, EF., Wang, Y., Marron, D., Trilhe, J. (1989). A Reconfigurable SRAM 4.5 Mbit WSI Memory. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_21
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_21
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