Introduction

Abstract

Latchup is a key concern to bulk CMOS. It stems from parasitic bipolar transistors, which are structurally inherent to bulk CMOS. These transistors can be activated in various ways, and as CMOS technologies are scaled down, both in dimension and in circuit delay, this variety grows. Under certain conditions the activated transistors can dominate circuit behavior. However, with proper process and layout design, CMOS chips can be operated under relatively harsh conditions without ever encountering latchup. What is proper can vary with application — the type of chip, its performance, package, allowable cost, etc. This book will provide the insight — as well as some useful analysis, characterization, and avoidance techniques — for assessing what is proper in each application.