Abstract
According to the design methodology outlined in the previous chapters, system-level synthesis is the design step dealing with a system represented at the highest abstraction level. At this level the specification is formulated as a set of interacting processes, and the basic system components considered during this design step are processors, ASICs, memories, buses, etc. Thus, system-level synthesis operates at the highest level of system design where fundamental decisions are taken which have great influence on the structure, cost and performance of the designed system.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1998 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Eles, P., Kuchcinski, K., Peng, Z. (1998). System-Level Synthesis. In: Eles, P., Kuchcinski, K., Peng, Z. (eds) System Synthesis with VHDL. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2789-0_4
Download citation
DOI: https://doi.org/10.1007/978-1-4757-2789-0_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5024-6
Online ISBN: 978-1-4757-2789-0
eBook Packages: Springer Book Archive