Abstract
The driving force behind the spectacular advancement of the integrated circuit technology in the past thirty years has been the exponential scaling of the transistor feature size, i.e., the minimum dimension of a transistor. It has been following the Moore’s Law [1] at the rate of a factor of 0.7 reduction every three years. It is expected that such exponential scaling will continue for at least another 10 to 12 years as projected in the 1997 National Technology Roadmap for Semiconductors (NTRS’97) [2] shown in Table 1.1
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Cong, J. (2001). Interconnect Planning. In: Lu, B., Du, DZ., Sapatnekar, S.S. (eds) Layout Optimization in VLSI Design. Network Theory and Applications, vol 8. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3415-7_2
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DOI: https://doi.org/10.1007/978-1-4757-3415-7_2
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