Nyquist-rate Converters: An Overview

Abstract

Digital-to-analog and analog-to-digital converters are among the most important technology enablers for integrated circuits for communication applications. From a theoretical point of view, and in order to better study the different architectures, it is convenient to consider data converters as stand-alone IP (Intellectual Property) building blocks, and classify them according to the most important principles of operation. This leads us, for the sake of simplicity, and as it has been done in the current textbook, to define two main categories: Nyquist-rate and oversampled converters. This extreme simplification needs, however, some clarifications, that will be carried out in the paragraph dedicated to the converters architectures. Moreover, the “stand-alone IP-block” assumption should not lead to misleading interpretations, since in practical applications it is highly improbable to find spare ADCs or DACs used as stand-alone cells, to implement self-consistent functions. On the contrary, and especially in Systems-On-Chips (SOCs), ADCs and DACs are the core elements of much more highly integrated functions where, around the key operation of converting data from the analog (digital) domain to the digital (analog) domain, a number of other vital operations are implemented as well: i) integrate those building blocks that are indispensable for the converter to work properly (bandgap references, current references, reference buffers), ii) interface it to the external world (input buffers, programmable gain amplifiers, output buffers, power amplifiers, line drivers), iii) ensure proper conditions to reach a target performance (dc-dc converters, high PSRR voltage regulators, low jitter phase-locked loops), iv) provide a number of additional features to complete the functionality of the overall data conversion channel (antialiasing, reconstruction filtering, analog and/or digital channel filtering, serial/parallel I/O ports, offset compensation, overflow detection, power-up-down management, thermal protection, ...), and finally, sometimes neglected but extremely important, v) add that hardware overhead which allows a complete and cost effective testability of the system (SCAN test, BIST analog,...). Given a specific application, which determines consequently a specification for the whole data conversion system in terms of static and dynamic parameters (power supply, current consumption, power supply rejection ratio, integral and differential non-linearity, signal-to-noise ratio, total-harmonic distortion,...), the converter of choice will fall within a restricted number of architectures: oversampled or Nyquist rate, and in the last case slow speed, very high resolution (dual ramp, incremental), or medium speed, n-clock cycles (algorithmic, successive approximation), or finally very high speed, 1–2 clock cycles converters (pipeline, two-step flash, full flash, folding). Usually the data converter represents the most difficult building block to be developed, and the key knowledge of the designer concerning one of its possible architectures, determines not only the choice of the converter itself, but also the development of all remaining auxiliary functions around it. The specification of the data conversion channel directly translates into the one of the converter, and the auxiliary blocks have to be properly sized, in order to guarantee and preserve the full performance. The example of Fig. 1.1 can help to gain a more in depth understanding of the subject.