Abstract
Now comes the “hard” part. The next three chapters are all about hardware, which covers a wide gamut of topics like FPGA, SOPC, LCD, etc. This chapter begins with an overview of the embedded hardware in general, followed by detailed discussions about FPGA and IP protection.
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Notes
- 1.
So far there are still no systematic approaches to reliably verify or prove the correctness of asynchronous design.
- 2.
For example, process(all) is not supported by Modelsim until version 10.0.
- 3.
For the sake of one-hot encoding, a reversed case statement is adopted where 1'b1 is put in the case expression. A reverse case statement is good for synthesis because only the active FF is compared instead of the whole vector (Ref [10]).
- 4.
In Verilog 2001, wildcard is supported by using always @(*). In VHDL 2008, it is supported by using process(all).
- 5.
Note that metal case/DIP is not the only package available. The oscillator could be in any package, such as a plastic case with a surface mount package.
- 6.
The solution described here mainly applies to Altera FPGAs. But I guess similar setups can be found for devices from other FPGA vendors.
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Gu, C. (2016). Field-Programmable Gate Arrays. In: Building Embedded Systems. Apress, Berkeley, CA. https://doi.org/10.1007/978-1-4842-1919-5_9
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