Abstract
The electrical performance (such as electrical resistance, inductance, and capacitance) is a key factor for a WLCSP product. Many studies, such as the electrical performance of different devices, effect of assembly reflow process on electrical properties, and the resistance of a solder joint, have been done to improve a product’s electrical performance [1–3]. In recent years, the investigation for the electrical performance of a WLCSP has been paid more attention due to the wide applications of the WLCSP. The parasitic resistance, inductance, and capacitance (RLC) will impact the efficiency and switch speed of the WLCSP circuit. The electromigration issue of WLCSP, which is a multi-physics problem, becomes more critical due to the high current density in analog and power electronics. This chapter will introduce the electrical parasitic RLC simulation and electromigration simulation methods for WLCSP and wafer level interconnects.
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Qu, S., Liu, Y. (2015). Electrical and Multiple Physics Simulation for Analog and Power WLCSP. In: Wafer-Level Chip-Scale Packaging. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-1556-9_8
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DOI: https://doi.org/10.1007/978-1-4939-1556-9_8
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