Skip to main content

Bipolar and Junction Field-Effect Transistors

  • Chapter
  • First Online:
Silicon Analog Components
  • 1810 Accesses

Abstract

Bipolar junction transistors (BJT) are inherent to CMOS technologies. Understanding the basic principles of operation of a BJT and its characteristics is not only important to efficiently use the component in Bipolar-CMOS (BiCMOS) applications. It is also important to understand bipolar effects in CMOS, such as subthreshold behavior, snapback, and latch-up, and to identify process and design techniques to modify their impact on circuit performance. Similarly, a discussion of integrated Junction field-effect transistors (JFET) is important to its use in analog designs, mainly as a very low-noise, high input-impedance device. It is also important to understand its parasitic effect, referred to as “The JFET Effect” in high-voltage, high power devices. The chapter begins with a review of BJT types, operation, and characteristics that are relevant to analog applications. This is followed by a description of JFET types, basic operation, and characteristics. The chapter concludes with simple circuit applications of both transistors.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Recall that at ohmic contacts, carriers are at thermal equilibrium.

  2. 2.

    \(h_{\text{fe}}\) stands for hybrid model, forward-active mode, common emitter.

  3. 3.

    Patterning, implanting, silicidation, and other unit processes are described in [2].

References

  1. A. B. Phillips, Transistor Engineering, McGraw-Hill, 1962.

    Google Scholar 

  2. B. El-Kareh, Fundamentals of Semiconductor Processing Technologies, Kluwer Academic Publishers,1995.

    Google Scholar 

  3. P. J. Coppen and W.T. Matzen, “Distribution of recombination current in emitter-base junctions of silicon transistors,” IEEE Trans. Electron Dev., ED-9 (1), 75-81, 1962.

    Google Scholar 

  4. C. T. Sah, “Effect of surface recombination and channel on p-n junction and transistor characteristics,” IEEE Trans. Electron Dev., ED-9 (1), 94-108, 1962.

    Google Scholar 

  5. C. T. Sah, R. N. Noyce, and W. Shockley, “Carrier generation and recombination in p-n junctions and p-n junction characteristics,” IRE Trans. Electron Dev., 45 (9) 1228-1238, 1957.

    Google Scholar 

  6. G. D. Mahan, “Energy gap in Si and Ge: Impurity dependence,” J. Appl. Phys., 51 (5), 2634-2646, 1980.

    Google Scholar 

  7. T. N. Morgan, “Broadening of impurity bands in heavily doped silicon,” Phys. Rev., 139, 343-348, 1965.

    Google Scholar 

  8. R. J. Van Overstraeten, H. J. DeMan, and R. P. Mertens, “Transport equation in heavily doped silicon,” IEEE Trans. Electron Dev., ED-20 (3), 290-298, 1973.

    Google Scholar 

  9. H. P. D. Lanyon and R. A. Tuft, “Bandgap narrowing in moderately to heavily doped silicon,” IEEE Trans. Electron Dev., ED-26 (7), 1014-1018, 1979.

    Google Scholar 

  10. J. W. Slotboom and H. C.. DeGraaff, “Bandgap narrowing in silicon bipolar transisotrs,” IEEE Trans. Elecron Dev., ED-24, (8), 1123-1125, 1977.

    Google Scholar 

  11. J. del Alamo, S. Swirhun, and R. M. Swanson, “Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon,” IEEE IEDM Tech. Digest, 290-293, 1985.

    Google Scholar 

  12. E. J. McGrath and D. H. Navon, “Factors limiting current gain in power transistors,” IEEE Trans. Electron Dev., ED-24 (10), 1255-1259, 1977.

    Google Scholar 

  13. B. El-Kareh, Silicon Devices and Process Integration, Chap. 3, p. 167, Springer, 2009.

    Google Scholar 

  14. A. Hastings, The Art of Analog Layout, pp. 312-313, Pearson Prentice Hall, 2006.

    Google Scholar 

  15. W. M. Webster, “On the variation of junction transistor current amplification factor with emitter current,” Proc. IRE, 42 (6), 914-920, 1954.

    Google Scholar 

  16. C. T. Kirk, Jr., “A Theory of transistor cut-off frequency fall-off at high current densities,” IEEE Trans Electron Dev., ED-9 (2), 164-174, 1962.

    Google Scholar 

  17. S. K. Ghandhi, The Theory and Practice of Microelectronics, John Wiley and Sons, 1968.

    Google Scholar 

  18. Y. S. Yuan, “Base current reversal in bipolar transistors and circuits: a review and update,” IEE Proc.-Circuits Syst., 141 (4) 299-306, 1994.

    Google Scholar 

  19. J. M. Early, “Effects of space-charge layer widening in junction transistors,” Proc. IRE, 40, 1401-1406, 1952.

    Google Scholar 

  20. H. K. Gummel, “A charge control relation for bipolar transistors,” Bell Syst. Tech. J., 49, 115-120, 1970.

    Google Scholar 

  21. E. J. Prinz and J. C. Sturm, “Analytical modeling of current gain – Early voltage products in Si/Si1-xGex/Si heterojunction bipolar transistors,” IEEE IEDM Tech. Digest, 853-856, 1991.

    Google Scholar 

  22. L. J . Giacoletto, “Study of p-n-p alloy junction transistor from d-c through medium frequencies,” RCA Rev., 15 (4), 506-562, 1954.

    Google Scholar 

  23. R. J. Baker, CMOS, Design, Layout, and Simulation, J. Wiley & Sons, Inc., 2010.

    Google Scholar 

  24. P. R. Gray, P. J. Hurst, S. H Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 2001.

    Google Scholar 

  25. D. F. Hilbiber, “A new semiconductor voltage standard,” IEEE ISSCC, Digest Tech. Papers, 32-33, 1964.

    Google Scholar 

  26. R. J. Widlar, “New developments in IC voltage regulators,” IEEE ISSCC, Digest Tech. Paper, 158-159, 1970.

    Google Scholar 

  27. A. P. Brokaw, “A simple three-terminal IC bandgap reference,” IEEE, J. Solid-State Circuits, SC-9 (6), 388-393, 1974.

    Google Scholar 

  28. C. R. Palmer and R. C. Dobkin, “A curvature corrected voltage reference,” ISSCC, 58-59, 1981.

    Google Scholar 

  29. G. C. M. Meijer, P. C. Schmale, and K. van Zalinge, “A new curvature corrected bandgap reference,” IEEE JSSC, SC-17 (6), 1139-1143, 1982.

    Google Scholar 

  30. B.-S. Song and P. R. Gray, “A precision curvature-compensated CMOS bandgap reference,” IEEE JSSC, SC-18 (6), 634-643, 1983.

    Google Scholar 

  31. V. V. Ivanov, K. E. Sanborn, I. M. Filanovsky, “Bandgap voltage references with 1 V supply,” ESSCIRC, 311-314, 2006.

    Google Scholar 

  32. M. A. P. Pertijs, G. C. M. Meijer, and J. H. Huijsing, “Precision temperature measurement using CMOS substrate PNP transistors,” IEEE Sensors J., 4 (3), 294-300 m 2004.

    Google Scholar 

  33. V.A. Vashchenko, D.J. LaFonteese, and K. G. Korablev, “Lateral PNP BJT ESD Protection Devices,” IEEE BCTM, 53-56, 2008.

    Google Scholar 

  34. W. Shockley, “A unipolar ‘field-effect’ transistor,” Proc. IRE, 40 (11), 1367-1376, 1952.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Badih El-Kareh .

Problems

Problems

The temperature is 300 K unless otherwise stated.

  1. 1.

    In an NPN transistor operated in the forward-active mode, the base current is 10 nA and the emitter current 0.61 μA.

    1. (a)

      Neglect leakage current and find α and β.

    2. (b)

      The transistor is subjected to an accelerated aging stress, and β is found to drop to 29.5 at the same emitter current. Assume that β degradation is solely due increased emitter–base leakage after stress and calculate the leakage.

  2. 2.

    An NPN transistor has a uniform total emitter area of 50 μm2. A forward voltage V BE = 0.7 V is applied to the base–emitter junction and a reverse voltage V CE = 5 V to the collector–base junction. The base and emitter currents are measured at, respectively, 1 and 61 μA. Assume low-level injection and determine

    1. (a)

      The injection ratio.

    2. (b)

      The emitter current density.

    3. (c)

      The saturation current of the emitter–base junction.

    4. (d)

      The collector current for a forward bias V BE = 0.75 V.

  3. 3.

    Show that the condition α 1 + α 2 is equivalent to β 1 β 2.

  4. 4.

    The uniform doping concentrations in the emitter, base, and collector of an NPN transistor are, respectively, N D = 1020, N A = 2 × 1017, and N D = 8 × 1016 cm−3. The metallurgical base width is 0.8 μm and the emitter area is 10 μm2. The base–emitter junction is forward-biased at V BE = 0.6 V and the collector–base junction reversed-biased at 5 V.

    1. (a)

      Find the electrical base width W b.

    2. (b)

      The minority electron concentration at the depletion boundary of the emitter–base junction.

    3. (c)

      The total charge of minority-carrier electrons in the base.

  5. 5.

    The externally applied collector voltage in a grounded-emitter NPN is fixed at 1.5 V and the base–emitter junction gradually forward-biased. At V BE = 0.6 V, the collector current is 100 nA. For a total collector resistance of 1 kΩ, find V BE at the onset of saturation. Assume low-level injection and neglect emitter and base resistances.

  6. 6.

    Consider the NPN transistor in the following circuit. Neglect leakage currents.

    1. (a)

      Find the collector and base currents for α = 0.95.

    2. (b)

      Calculate the reverse voltage seen at the collector–base junction.

  7. 7.

    The base and collector of an NPN transistor are uniformly doped at a concentration N A = N D = 2.5 × 1017 cm−3 and the emitter is degenerately doped. The distance between collector–base and emitter–base metallurgical junctions is 0.2 μm. The emitter is shorted to the base and the reverse collector voltage gradually increased. Will punch-through or avalanche breakdown occur first?

  8. 8.

    Show that for a transistor in the forward-active mode, β is approximately proportional to the intrinsic base sheet resistance.

  9. 9.

    A transistor is fabricated with an exponential base profile having a concentration of 5 × 1018 cm−3 at the emitter–base depletion boundary and 1017 cm−3 at the collector–base depletion boundary in the base. The base width W b is 0.1 μm. For V CE = 1 V, V BE = 0.7 V calculate:

    1. (a)

      The base sheet resistance

    2. (b)

      The built-in field in the base

    3. (c)

      The minority-carrier drift velocity in the base

    4. (d)

      The base transit time.

  10. 10.

    In a PNP transistor, the collector current is kept constant, while the temperature is increased. I B decreases in magnitude, passes through zero, and changes polarity. What physical effects account for this behavior?

  11. 11.

    Assume that an external resistor is placed in either the base lead or the emitter lead in a bipolar transistor of the type shown in Fig. 5.7. Which placement has the largest effect on the collector current I C?

  12. 12.

    The emitter and base regions of an NPN transistor are uniformly doped with N D = 1018 cm−3 and N A = 1017 cm−3.

    1. (a)

      What are the thermal equilibrium minority and majority concentrations in the neutral regions?

    2. (b)

      Find the built-in voltage and depletion-layer width?

    3. (c)

      A forward voltage V BE = 0.6 V is applied to the junction. Neglect series resistances and find the excess electron and hole concentrations at the depletion edges of the emitter–base junction.

    4. (d)

      What are the percentile increases in the minority- and majority-carrier concentrations at those boundaries?

    5. (e)

      Repeat (c) and (d) for a forward voltage V BE = 0.82 V.

  13. 13.

    Consider two N+P junctions formed at a distance 0.1 mm apart on a P-type substrate having a uniform concentration N A = 1015 cm−3. The electron lifetime in the P-type substrate is 10 μs.

    1. (a)

      Find the electron diffusion length in the substrate.

    2. (b)

      Do you expect this structure to exhibit bipolar action?

    3. (c)

      One of the junctions is forward-biased at V F = 0.6 V and the other reverse-biased at V R = 10 V.

      1. (i)

        Estimate the electron current density in the substrate.

      2. (ii)

        Calculate the excess electron current density in the substrate at the depletion edge of the forward-biased junction.

      3. (iii)

        Is the forward-biased junction in the high-level injection mode? Explain.

  14. 14.

    In a PNP transistor, the emitter current is I E = 10 mA at V BE = 0.7 V.

    1. (a)

      Neglect series resistances and calculate the saturation current at 25 °C.

    2. (b)

      Calculate the absolute change and percentile changes in V F as I E is varied by ± 75 % from its initial value at 0.7 V.

    3. (c)

      Find the saturation current at 85 °C.

  15. 15.

    The base width in an NPN transistor is 1.0 μm and the doping concentrations in the emitter, base, and collector are, respectively, N D = 1020, N A = 1 × 1016, and N D = 1017 cm−3. The emitter and base are shorted and the collector reverse-bias voltage increased. Will punch-through or avalanche breakdown occur first?

  16. 16.

    In an NPN transistor operated in the forward-active mode, the emitter-base capacitance is C jE ≅ 2 fF and the base width is W b = 0.5 μm. The concentration in the base is 6 × 1017 cm−3. Assume that the cutoff frequency f T is limited only by the emitter delay and base transit time and estimate f T at I E = 1 μA and I E = 1 mA.

  17. 17.

    Self-heating is the increase in transistor temperature during operation as a result of insufficient dissipation of power generated by the transistor. A transistor operates in the forward-active mode, and its temperature rises gradually as the collector voltage is increased.

    1. (a)

      For a constant V BE, how does the increase in temperature affect I C and I B?

    2. (b)

      How would V BE be affected if I B is kept constant as the temperature increases?

  18. 18.

    The emitter–base junction x jE and collector–base junction x jC of an NPN transistor are, respectively, 0.45 and 0.71 μm deep. The emitter, base, and collector are uniformly doped with, respectively, N D = 1020 cm−3, N A = 1017 cm−3, N D = 1017 cm−3. The base current density at V BE = 0.6 V is 3.23 × 10−3 A/cm2.

    1. (a)

      Estimate the NPN gain β at V CE = 1 V.

    2. (b)

      What is the maximum V CE that can be applied? What mechanism(s) limit this value?

    3. (c)

      Where such a transistor would be used?

  19. 19.

    In a double-gated PJFET, the channel and gate concentrations are N A = 1016 cm−3 and N D = 1020 cm−3. Calculate the distance between the gate metallurgical junctions that will give a turn-off gate-to-source voltage V G = 1.4 V.

  20. 20.

    In a double-gated NJFET, the channel and gate concentrations are N D = 1016 cm−3 and N A = 1020 cm−3. The channel depth is 2a = 0.4 μm. Is the transistor on or off at V G = 0?

  21. 21.

    An NJFET is constructed on a P-substrate which acts as a back gate and is held at ground. The doping concentrations in the channel, top gate, and substrate are, respectively, N D = 2.5 × 1016 cm−3, N A = 1020 cm−3, and N A = 1016 cm−3. The channel dimensions are a = 0.3 μm, W = 20 μm, and L = 10 μm.

    1. (a)

      Calculate the drain current for V G = 0 and V D = 0.1 V.

    2. (b)

      Find V Dsat for the top-gate voltage V G = 0 and V G = −1 V.

    3. (c)

      At what top-gate voltage does the channel conductance gD to zero?

  22. 22.

    In a symmetrical double-gated PJFET, the channel and gate concentrations are uniform with N A = 1016 cm−3 and N D = 1020 cm−3. The channel length, width, and metallurgical thickness are, respectively, 4 μm, 4 μm, and 0.76 μm. What gate voltage will yield a JFET resistance of 205 kΩ? Assume V D = 0.1 V and neglect source and drain series resistances.

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer Science+Business Media New York

About this chapter

Cite this chapter

El-Kareh, B., Hutter, L.N. (2015). Bipolar and Junction Field-Effect Transistors. In: Silicon Analog Components. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2751-7_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4939-2751-7_5

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4939-2750-0

  • Online ISBN: 978-1-4939-2751-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics