Abstract
Traditional evolutionary fault-tolerant scheme can effectively repair circuit faults, but for large-scale integrated circuits, the evolution process consumes a lot of time and it is difficult to meet the real-time requirements. In this paper, a real-time system fault-tolerant scheme based on improved chaotic genetic algorithm is proposed. The scheme uses a built-in test detection mechanism with feedback to detect the running state of the circuit in real time. When a fault occurs, normal system operation is maintained by the fault compensation mechanism. At the same time, the system uses the evolution repair mechanism to repair the faulty circuit. Evolution process uses an improved chaotic genetic algorithm, which can quickly converge to obtain a repair circuit through adaptive chaotic crossover and mutation. This paper builds a fault-tolerant system on the FPGA. In the experiment, the fault is randomly injected into circuit so that to simulate the actual circuit fault. The proposed algorithm and fault-tolerant scheme are used to verify the self-repairing ability of the system. The experimental results show that under real-time constraints, the repair rate of the fault circuit reaches 94%.
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Funding
This work was supported by the National Nature Science Foundation of China (No.61472100) and Fundamental Research Funds for the Central Universities, China (No. DUT17JC26).
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© 2019 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Wang, J., Kang, J., Hou, G. (2019). Real-Time System Fault-Tolerant Scheme Based on Improved Chaotic Genetic Algorithm. In: Jia, M., Guo, Q., Meng, W. (eds) Wireless and Satellite Systems. WiSATS 2019. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 281. Springer, Cham. https://doi.org/10.1007/978-3-030-19156-6_14
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DOI: https://doi.org/10.1007/978-3-030-19156-6_14
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