Abstract
In this paper, FPGA implementation of a LFSR and PSEUDO_NOISE(PN) sequences are designed and carried out for many purposes. The motivation for that is multifold: LFSR and related PN sequences are indispensable building blocks not only for cipher sequence used in cryptography, steganography but also for BIST (build in self test system), scrambler. There have been a lot of attempts to develop specific circuit and sequences for these applications. However, the interleaving approach renders the optimal products in term of sequences length, statistical properties (distributions, autocorrelation function(ACF) and linear complexity (LC). It will be shown that the Interleaving structure can be easily expressed in time-multiplexing technique (namely Delay operation-D-transform). The equivalence between the D-transform and other well-known methods will be also highlighted in this contribution. Furthermore, the interleaving structure with outstanding LC will be given.
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Son, N.V., Quynh, L.C., Kien, T.V., Du, D.H., Hoa, D.K. (2020). FPGA Implementation of Optimal PN_Sequences by Time_Multiplexing Technique. In: Sattler, KU., Nguyen, D., Vu, N., Tien Long, B., Puta, H. (eds) Advances in Engineering Research and Application. ICERA 2019. Lecture Notes in Networks and Systems, vol 104. Springer, Cham. https://doi.org/10.1007/978-3-030-37497-6_44
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DOI: https://doi.org/10.1007/978-3-030-37497-6_44
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