Abstract
In this chapter we will detail the key advantages of Body-Bias for digital design. As Body-Bias modulates the transistors’ V T, it enables higher I on at the expense of higher I off. This design tuning knob can be used to either increase yield (more dies within design specifications), or to extend the operating performance (with lower voltage, higher speed, or lower power). Increased yield can be brought directly by die acceleration, while indirect leakage gains can be obtained through increased transistor drive of slowest transistors at slowest process corner. Similarly, indirect dynamic power reduction can be obtained thanks to lower operating voltage. As some of these gains require trade-off, such as increased speed at low temperature vs. higher leakage at maximum temperature, the circuit architect can either find the best trade-off between these aspects and/or implement system operating modes. This chapter describes how to modulate the Body-Bias (i.e., the bias law and the bias limits) from a design perspective to take full advantage of this tuning capability.
FD-SOI Body-Bias enables software defined V T
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Notes
- 1.
More on this design space evolution with Body-Bias in Chap. 16.
- 2.
Further abbreviated qFO4, see Fig. 3.2 and next section for an explanation of quasi-fan-out-of-4 logic path and why we call it ‘quasi’.
- 3.
Hence the ‘quasi’ fan-out-of-4.
- 4.
The internal energy is the energy driven by the cell with input and output capacitance load energy excluded.
- 5.
Implicit bias maximum applied at slowest RTL synthesis PVT, kindly refer to Sect. 16.3.
- 6.
Kindly refer to Chap. 16 for implementation corners definition.
- 7.
Because there is a race between the global cell undersize and individual cell leakage, we denote this leakage reduction as ‘indirect’.
- 8.
Kindly refer to Appendix B in case you are not familiar with digital constraints.
- 9.
Gate overdrive voltage.
- 10.
- 11.
In situations of high temp skewed corners, SRAM bitcell has their stability weakened by V T shift induced by Forward Body-Bias, see Chap. 5.
- 12.
In FD-SOI V T modulation can be done by transistors WELLs, LVT transistors have their NMOS in NWELL and PMOS is PWELL. Refer to Chap. 2.
- 13.
Emphasized for the reader to understand that there is a trade-off to make here.
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Clerc, S., Gomez, R.G. (2020). Body-Bias for Digital Designs. In: Clerc, S., Di Gilio, T., Cathelin, A. (eds) The Fourth Terminal. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-39496-7_3
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