Abstract
Squeak is an open source Smalltalk-80 implementation created to implement high level code that is used as glue between optimized, low level ”plug-ins” written in C or a restricted subset of Smalltalk and translated to C. SiliconSqueak is a hardware implementation with coarse grained processors for the high level code and fine grained “ALU Matrix” co-processors for the plug-ins. When implemented in an FPGA, a given area can either be used for a co-processor or for two more high level cores. The ideal mix varies at runtime as applications go through different phases, so the solution presented in this paper is to reconfigure the system as needed.
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References
Bouwens, F.J., Berekovic, M., Kanstein, A., Gaydadjiev, G.N.: Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. In: Proceedings of International Workshop on Applied Reconfigurable Computing, pp. 1–13 (2007)
Goldberg, A., Robson, D.: Smalltalk-80: the language and its implementation. Addison-Wesley Longman Publishing Co., Inc., Boston (1983)
Hölzle, U.: Adaptive optimization for Self: reconciling high performance with exploratory programming. Ph.D. thesis, Stanford University (1994)
Ingalls, D., Kaehler, T., Maloney, J., Wallace, S., Kay, A.: Back to the future: The story of Squeak, A practical Smalltalk written in itself. In: Proceedings OOPSLA 1997, ACM SIGPLAN Notices, pp. 318–326. ACM Press (1997)
Kyo, S., Koga, T., Hanno, L., Nomoto, S., Okazaki, S.: A low-cost mixed-mode parallel processor architecture for embedded systems. In: Proceedings of the 21st Annual International Conference on Supercomputing - ICS 2007, p. 253. ACM Press, New York (2007), http://portal.acm.org/citation.cfm?doid=1274971.1275006
Schoeberl, M.: A Java Processor Architecture for Embedded Real-Time Systems. Journal of Systems Architecture (2007), doi:10.101
So, H.K.H.: BORPH: An Operating System for FPGA-Based Reconfigurable Computers. Ph.D. thesis, Engineering – Electrical and Computer Sciences, University of California, Berkeley (2007)
Williams, I.W.: Using FPGAs to Prototype New Computer Architectures. In: Moore, W.R., Luk, W. (eds.) FPGAs, ch. 6.8, pp. 373–382. Abingdon EE & CS Books (1991)
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de Assumpção, J.M., Voswinkel, M., Marques, E. (2014). Adapting Processor Grain via Reconfiguration. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_27
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DOI: https://doi.org/10.1007/978-3-319-05960-0_27
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