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Introduction

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Low-Noise Low-Power Design for Phase-Locked Loops

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Abstract

Phase-locked loop (PLL) circuits are widely used to generate a precise frequency signal from a very high precision reference signal. It has wide application in wired and wireless communication systems to provide accurate carrier that is phase aligned with the incoming high-precision reference clock signal. The voltage-controlled oscillator (VCO) signal is divided and compared with the high-precision reference by the phase frequency detector (PFD). Then, the error signal is fed into a charge pump to transform the phase error detected by the PFD into current pulses. The pulses are filtered by the loop filter and then the filtered voltage is used to control the VCO to stabilize its phase and frequency variations. The negative feedback mechanism around the PLL loop results in the generation of a tunable and stable output signal at the desired frequency.

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Authors and Affiliations

  1. Santa Clara, California, USA

    Feng Zhao

  2. Department of Electrical and Computer En, Auburn University, Auburn, Alabama, USA

    Fa Foster Dai

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  1. Feng Zhao
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  2. Fa Foster Dai
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Correspondence to Feng Zhao .

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Zhao, F., Dai, F. (2015). Introduction. In: Low-Noise Low-Power Design for Phase-Locked Loops. Springer, Cham. https://doi.org/10.1007/978-3-319-12200-7_1

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  • DOI: https://doi.org/10.1007/978-3-319-12200-7_1

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-12199-4

  • Online ISBN: 978-3-319-12200-7

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