Chaotic DDEs: FPGA Examples and Synchronization Applications

Abstract

This chapter explores particular advantage(s) of FPGAs for investigating nonlinear dynamics—realization of time delayed chaotic systems. These advantages are the availability of on-chip memory and the fact that generate statements in VHDL can be used to elegantly implement arbitrary (limited by on-chip memory and the number of FPGA logic elements) length delay chains. We will also explore synchronization applications in chaotic DDEs using the FPGA.

Valli et al. Synchronization in Coupled Ikeda Delay Systems: Experimental Observations using FPGAs [7]

Appendices

Problems

5.1

Consider the Ikeda DDE:

$$\begin{aligned} \dot{x}&=\mu \sin (x(t-\tau ))-\alpha x(t) \end{aligned}$$

(5.14)

$\mu =6, \tau =1,\alpha =1$.

Perform a ModelSim simulation of the system above.

5.2

One approach to speed up the synthesis procedure is to minimize the number of delays by increasing the sampling frequency of the system. Explore this approach by increasing the sampling frequency for, say, the Ikeda system.

5.3

One of the earliest and most widely studied DDE is the Mackey-Glass equation [6], shown in Eq. (5.15).

$$\begin{aligned} \dot{x}&=\frac{ax(t-\tau )}{1+x(t-\tau )^c}-bx(t) \end{aligned}$$

(5.15)

Parameters for chaos: $a=3, b=1,c=7,\tau =3$ [6]. Implement the equation on the FPGA.

5.4

Implement the antisymmetric piecewise-linear DDE [6], shown in Eq. (5.16) on the FPGA. Use $\tau =3$.

$$\begin{aligned} \dot{x}&=|x(t-\tau ) + 1|-|x(t-\tau ) - 1| - x(t-\tau ) \end{aligned}$$

(5.16)

5.5

Implement the asymmetric piecewise-linear DDE [6], shown in Eq. (5.17) on the FPGA. Use $\tau =1.8$.

$$\begin{aligned} \dot{x}&= x(t-\tau )-2|x(t-\tau )|+1 \end{aligned}$$

(5.17)

5.6

Explore the synchronization schemes discussed in Sect. 5.4 using the DDEs from problems 5.3, 5.4 and 5.5.

5.7

Consider Eq. (5.18) [6].

$$\begin{aligned} \dot{x}&= \frac{1}{\tau }\int _0^\tau x(t-s)(4-|x(t-s)|)ds \end{aligned}$$

(5.18)

In Eq. (5.18), the time derivative depends on the average value of a function for time lags of $x_s$ from $s=0\text { to } \tau$. Implement the equation on an FPGA, using $\tau =3$.

5.8

Investigate bifurcation mechanisms in any of the DDEs from this chapter.

Lab 5: The Lang-Kobayashi Chaotic Delay Differential Equation

Objective: Simulate and physically realize the Lang-Kobayashi (L-K) chaotic DDE [2]

$$\begin{aligned} \frac{dE}{dt}&=-(1+i\alpha )|E|^2E+\eta _1E(t-\tau _1)+\eta _2E(t-\tau _2) \end{aligned}$$

(5.19)

Theory: Notice that Eq. (5.19) is in the complex domain. However we can separate the real and imaginary parts by writing $E(t)=\rho (t)e^{i\theta (t)}$ in Eq. (5.19) to obtain Eqs. (5.20) and (5.21).

$$\begin{aligned} \frac{d\rho }{dt}&=-\rho ^3+\eta _1\rho (t-\tau _1)\cos (\theta (t)-\theta (t-\tau _1))\nonumber \\&\quad +\eta _2\rho (t-\tau _2)\cos (\theta (t)-\theta (t-\tau _2)) \end{aligned}$$

(5.20)

$$\begin{aligned} \rho \frac{d\theta }{dt}&=-\alpha \rho ^3+\eta _1\rho (t-\tau _1)\sin (\theta (t)-\theta (t-\tau _1))\nonumber \\&\quad +\eta _2\rho (t-\tau _2)\sin (\theta (t)-\theta (t-\tau _2)) \end{aligned}$$

(5.21)

Verify that one can indeed obtain Eqs. (5.20) and (5.21) from Eq. (5.19).

Lab Exercise:

• 1. Simulate (using Simulink and Modelsim), verify using SignalTap and hence implement Eqs. (5.20) and (5.21) for the following parameters $\alpha =4, \eta _1=3.5, \eta _2=3, \tau _1=2.5, \tau _2=0.1$.

• 2. Study synchronization mechanisms in the L-K DDE using the ideas from Sect. 5.4.