Abstract
This chapter presents a design automation approach that generates automatically error-free area and parasitic optimized layout views of output power stages consisting of multiple power MOSFETs. The tool combines a multitude of constraints associated with DRC, DFM, ESD rules, current density limits, heat distribution, and placement. It uses several optimization steps based on evolutionary computation techniques that precede a bottom-up layout construction of each power MOSFET, its optimization for area and parasitic minimization, and its optimal placement within the output stage power topology network.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Liew, B.K., Cheung, N.W., Hu, C.: Effects of self-heating on integrated circuit metallization lifetimes. In: IEDM Technical Digest., Washington, pp. 323–326 (1989)
Semenov, O., Vassighi, A., Sachdev, M.: Impact of Self-Heating Effect on Long-Term Reliability and Performance Degradation in CMOS Circuits. IEEE Trans. Device Mater. Reliab. 6(1), 17–27 (2006)
Tam, W.C., Blanton, S.: To DFM or not to DFM? In: IEEE Proceedings of the 48th Design Automation Conference, pp. 65–70, June 2011
Tien, L.C., Tang, J.J., Chang, M.C.: An automatic layout generator for I/O cells. In: Proceedings of the 5th International Workshop on System-on-Chip for Real-Time Applications, pp. 295–300, July 2005
Ming, C., Na, B.: An efficient and flexible embedded memory IP compiler. In: Proceedings of International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 268–273, Oct 2012
Kelly, M., Servais, G., Diep, T., Lin, D., Twerefour, S., Shah, G.: A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices. In: Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, pp. 175–185, Sept 1995
Franell, E., Drueen, S., Gossner, H., Schmitt-Landsiedel, D.: ESD full chip simulation: HBM and CDM requirements and simulation approach. Adv. Radio Sci. 6(10), 245–251 (2008)
Suman, B., Kumar, P.: A survey of simulated annealing as a tool for single and multiobjective optimization. J. Oper. Res. Soc. 57, 1143–1160 (2006)
Alpert, C.J., Mehta, D.P., Sapatnekar, S.S. (eds.): Handbook of algorithms for physical automation. CRC Press, Boca Raton. ISBN:10: 0849372429, ISBN:13: 978–0849372421 (2009)
Martins, R., Lourenco, N., Horta, N.: LAYGEN II—automatic layout generation of analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11), 1641–1654 (2013)
Lall, P.: Tutorial: temperature as an input to microelectronics—reliability models. IEEE Trans. Reliab. 45(1), 3–9 (1996)
Pedram, M., Nazarian, S.: Thermal modeling, analysis, and management in VLSI circuits: principles and methods. Proc. IEEE 94(8), 1487–1501 (2006)
Bechtold, T., Rudnyi, E., Korvink, J.: Dynamic electro-thermal simulation of microsystems—a review. J. Micromech. Microeng. 15(11), R17–R31 (2005)
Batty, W., Christoffersen, C., Panks, A., David, S., Snowden, C., Steer, M.: Electrothermal CAD of power devices and circuits with fully physical time-dependent compact thermal modeling of complex nonlinear 3-d Systems. IEEE Trans. Compon. Packag. Technol. 24(4), 566–590 (2001)
Han, Y., Koren, I.: Simulated annealing based temperature aware floorplanning. J Low Power Electron. 3(2), 1–15 (2007)
Ardestani, E., Ziabari, A., Shakouri, A., Renau, J.: Enabling power density and thermal-aware floorplanning. In: Proceeding of Semiconductor Thermal Measurement and Management Symposium, pp. 302–307, Mar 2012
Song, T., Sturcken, N., Athikulwongse, K., Shepard, K., Lim, S.K.: Thermal analysis and optimization of 2.5-D integrated voltage regulator. In: IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, pp. 25–28 (2012)
Ning, P., Wang, F., Ngo, K.D.T.: Automatic layout design for power module. IEEE Trans. Power Electron. 481–487 (2013)
Logan, S., Guthaus, M.R.: Fast thermal-aware floorplanning using white-space optimization. 17th IFIP International Conference on Very Large Scale Integration, pp. 65–70 (2009)
Ng, W.T., Chang, M., Yoo, A., Langer, J., Hedquist, T., Schweiss, H.: High speed CMOS output stage for integrated DC-DC converters. In: Proceedings of 9th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1909–1912, Oct 2008
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Guilherme, D., Guilherme, J., Horta, N. (2015). Automatic Layout Optimizations for Integrated MOSFET Power Stages. In: Fakhfakh, M., Tlelo-Cuautle, E., Siarry, P. (eds) Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-19872-9_6
Download citation
DOI: https://doi.org/10.1007/978-3-319-19872-9_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-19871-2
Online ISBN: 978-3-319-19872-9
eBook Packages: Computer ScienceComputer Science (R0)