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Memristor-Based Logic Circuits

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Memristor-Based Nanoelectronic Computing Circuits and Architectures

Part of the book series: Emergence, Complexity and Computation ((ECC,volume 19))

Abstract

Amongst several emergent applications of the memristance switching phenomenon, the implementation of logic circuits is gaining considerable attention. Memristor-based logic circuits open new pathways for the exploration of advanced computing architectures as promising alternatives to conventional integrated circuit technologies. However, up to now no standard logic design methodology exists, since it is not immediately clear what kind of computing architectures would in practice benefit the most from the computing capabilities of memristors. This chapter addresses memristive logic circuit design and computational methodologies, aiming to approach this novel area of research while motivating for further research on innovative design strategies, which comply with emerging technologies. First, a summary of the most recognized memristive logic circuit design concepts is provided. Then two novel logic design paradigms are presented, which aim to address several drawbacks of other existing design concepts in the literature, and to facilitate the incorporation of memristors in currently established logic circuit architectures. Thus they could be promising candidates to be used in future electronic systems design. The proposed design paradigms are validated through SPICE-based simulations for a variety of complex combinational logic circuits.

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References

  1. Y.V. Pershin, M. Di Ventra, Neuromorphic, digital and quantum computation with memory circuit elements. Proc. IEEE 100(6), 2071–2080 (2012)

    Article  Google Scholar 

  2. E. Lehtonen, M. Laiho, CNN using memristors for neighborhood connections, in 12th International Workshop Cellular Nanoscale Network Application (CNNA), Berkeley, CA (2010)

    Google Scholar 

  3. K.H. Kim, S. Gaba, D. Wheeler, J.M. Cruz-Albrecht, T. Hussain, N. Srinivasa, W. Lu, A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 12(1), 389–395 (2012)

    Article  Google Scholar 

  4. G. Howard, E. Gale, L. Bull, B. de Lacy Costello, A. Adamatzky, Evolution of plastic learning in spiking networks via memristive connections. IEEE Trans. Evol. Comput. 16(5), 711–729 (2012)

    Article  Google Scholar 

  5. I. Vourkas, G.C. Sirakoulis, Nano-crossbar memories comprising parallel/serial complementary memristive switches. BioNanoScience 4(2), 166–179 (2014)

    Article  Google Scholar 

  6. H. Kim, M.P. Sah, C. Yang, T. Roska, L.O. Chua, Neural synaptic weighting with a pulse-based memristor circuit. IEEE Trans. Circ. Syst. I, Reg. Papers 59(1), 148–158 (2012)

    Google Scholar 

  7. S. Kim, H.Y. Jeong, S.K. Kim, S.Y. Choi, K.J. Lee, Flexible memristive memory array on plastic substrates. Nano Lett. 11(12), 5438–5442 (2011)

    Article  Google Scholar 

  8. E. Linn, R. Rosezin, S. Tappertzhofen, U. Bottger, R. Waser, Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology 23(305205) (2012)

    Google Scholar 

  9. E. Lehtonen and M. Laiho, Stateful implication logic with memristors, in IEEE/ACM Int. Symp. Nanoscale Architectures (NANOARCH), San Francisco, CA (2009)

    Google Scholar 

  10. J. Borghetti, Z. Li, J. Straznicky, X. Li, D.A.A. Ohlberg, W. Wu, D.R. Stewart, R.S. Williams, A hybrid nanomemristor/transistor logic circuit capable of self-programming. Proc. Nat. Acad. Sci. (PNAS) USA 106(6), 1699–1703 (2009)

    Google Scholar 

  11. J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, R.S. Williams, Memristive switches enable ‘stateful’ logic operations via material implication. Nature 464(7290), 873–876 (2010)

    Article  Google Scholar 

  12. M. Di Ventra, Y.V. Pershin, The parallel approach. Nat. Phys. 9, 200–202 (2013)

    Article  Google Scholar 

  13. S. Kvatinsky, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, Memristor-Based Material Implication (IMPLY) logic: design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2054–2066 (2014)

    Google Scholar 

  14. E. Lehtonen, J.H. Poikonen, M. Laiho, Implication logic synthesis methods for memristors, in IEEE Int. Symp. Circuits Syst. (ISCAS), Seoul, South Korea, (2012)

    Google Scholar 

  15. G. Ligang, F. Alibart, D.B. Strukov, Programmable CMOS/memristor threshold logic. IEEE Trans. Nanotechnol. 12(2), 115–119 (2013)

    Article  Google Scholar 

  16. I. Vourkas, G.C. Sirakoulis, Memristor-based combinational circuits: a design methodology for encoders/decoders. Microelectron. J. 45(1), 59–70 (2014)

    Article  Google Scholar 

  17. J.J. Yang, D.B. Strukov, D.R. Stewart, Memristive devices for computing. Nat. Nano. 8, 13–24 (2013)

    Article  Google Scholar 

  18. Vourkas, G.C. Sirakoulis, Recent progress and patents on computational structures and methods with memristive devices. Recent Pat. Electr. Electron. Eng. 6(2), 101–116 (2013)

    Google Scholar 

  19. E. Lehtonen, J.H. Poikonen, M. Laiho, Two memristors suffice to compute all Boolean functions. Electron. Lett. 46(3), 239–240 (2010)

    Article  Google Scholar 

  20. W. Zhao, D. Querlioz, J.O. Klein, D. Chabi, C. Chappert, Nanodevice-based novel computing paradigms and the neuromorphic approach, in IEEE Int. Symp. Circuits Syst. (ISCAS), Seoul, South Korea (2012)

    Google Scholar 

  21. International Technology Roadmap for Semiconductors (ITRS) (2013). Available: http://www.itrs.net/. Accessed June 2014

  22. Y.V. Pershin, M. Di Ventra, Memory effects in complex materials and nanoscale systems. Adv. Phys. 60(2), 145–227 (2011)

    Article  Google Scholar 

  23. C. Torrezan, J.P. Strachan, G. Medeiros-Ribeiro, R.S. Williams, Sub-nanosecond switching of a tantalum oxide memristor. Nanotechnology 22(48), 485203 (2011)

    Article  Google Scholar 

  24. S. Kvatinsky, N. Wald, G. Satat, A. Kolodny, U.C. Weiser, E.G. Friedman, MRL—Memristor Ratioed Logic, in 13th International Workshop on Cellular Nanoscale Network and Application (CNNA), Turin, Italy (2012)

    Google Scholar 

  25. J. Rajendran, H. Manem, R. Karri, G.S. Rose, Memristor based programmable threshold logic array, in IEEE/ACM International Symposium on Nanoscale Architecture (NANOARCH), Anaheim, CA (2010)

    Google Scholar 

  26. S. Paul, S. Bhunia, A scalable memory-based reconfigurable computing framework for nanoscale crossbar. IEEE Trans. Nanotechnol. 11(3), 451–462 (2012)

    Article  Google Scholar 

  27. G.S. Snider, P.J. Kuekes, R.S. Williams, CMOS-like logic in defective, nanoscale crossbars. Nanotechnology 15, 881–891 (2004)

    Article  Google Scholar 

  28. M.M. Ziegler, M.R. Stan, CMOS/nano co-design for crossbar-based molecular electronic systems. IEEE Trans. Nanotechnol. 2(4), 217–230 (2003)

    Article  Google Scholar 

  29. D.B. Strukov, K.K. Likharev, CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16(6), 888–900 (2005)

    Article  Google Scholar 

  30. Y.V. Pershin, M. Di Ventra, Solving mazes with memristors: a massively parallel approach. Phys. Rev. E 84, 046703 (2011)

    Article  Google Scholar 

  31. Y.V. Pershin, M. Di Ventra, Self-organization and solution of shortest-path optimization problems with memristive networks. Phys. Rev. E 88, 013305 (2013)

    Article  Google Scholar 

  32. I. Vourkas, G.C. Sirakoulis, Study of memristive elements networks. J. Nano Res. 27, 5–14 (2014)

    Article  Google Scholar 

  33. F. Jiang, B.E. Shi, The memristive grid outperforms the resistive grid for edge preserving smoothing, in European Conference on Circuits Theory and Design (ECCTD), Antalya, Turkey (2009)

    Google Scholar 

  34. Z. Ye, S.H.M. Wu, T. Prodromakis, Computing shortest paths in 2D and 3D memristive networks. 15 Mar 2013. Available: http://arXiv:1303.3927

  35. E. Linn, R. Rosezin, C. Kugeler, R. Waser, Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9(5), 403–406 (2010)

    Article  Google Scholar 

  36. I Vourkas, G.C. Sirakoulis, On the analog computational characteristics of memristive networks, in 20th IEEE International Conference on Electronics, Circuits, Systems (ICECS), Abu Dhabi (2013)

    Google Scholar 

  37. A.N. Whitehead, B. Russell, Principia Mathematica, vol. I(7) (Cambridge University Press, Cambridge, 1910)

    Google Scholar 

  38. R.H. Wilkinson, A method of generating functions of several variables using analog diode logic. IEEE Trans. Electron. Comput. EC-12(2), 112–129 (1963)

    Google Scholar 

  39. S. Muroga, Threshold Logic and its Applications, Hoboken, NJ (Wiley, USA, 1972)

    Google Scholar 

  40. R. Zhang, P. Gupta, L. Zhong, N.K. Jha, Synthesis and optimization of threshold logic networks with application to nanotechnologies, in Design Automation and Test in Europe Conference (DATE), Paris, France, 2004

    Google Scholar 

  41. V. Beiu, J.M. Quintana, M.J. Avedillo, VLSI implementations of threshold logic: a comprehensive survey. IEEE Trans. Neural Netw. 14(5), 1217–1243 (2003)

    Article  Google Scholar 

  42. Y. Leblebici, H. Ozdemir, A. Kepkep, U. Cilingiroglu, A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold logic gates. IEEE J. Solid-State Circuits 31(8), 1177–1183 (1996)

    Article  Google Scholar 

  43. I. Vourkas, G.C. Sirakoulis, A novel design and modeling paradigm for memristor-based crossbar circuits. IEEE Trans. Nanotechnol. 11(6), 1151–1159 (2012)

    Article  Google Scholar 

  44. J.R. Heath, P.J. Kuekes, G.S. Snider, R.S. Williams, A defect-tolerant computer architecture: opportunities for nanotechnology. Science 280(5370), 1716–1721 (1998)

    Article  Google Scholar 

  45. I. Vourkas, G.C. Sirakoulis, Nano-crossbar memories comprising parallel/serial complementary memristive switches. BioNanoScience 4(2), 166–179 (2014)

    Article  Google Scholar 

  46. A. Chen, Accessibility of nano-crossbar arrays of resistive switching devices, in 11th IEEE Conference on Nanotechnology (IEEE-NANO), Portland, OR (2011)

    Google Scholar 

  47. S. Shin, K. Kim, S.M. Kang, Analysis of passive memristive devices array: data-dependent statistical model and self-adaptable sense resistance for RRAMs. IEEE Proc. 100(6), 2021–2032 (2012)

    Article  Google Scholar 

  48. J. Liang, H.-S.P. Wong, Cross-point memory array without cell selectors—Device characteristics and data storage pattern dependencies. IEEE Trans. Electron. Devices 57(10), 2531–2538 (2010)

    Article  Google Scholar 

  49. M.A. Zidan, H.A.H. Fahmy, M.M. Hussain, K.N. Salama, Memristor-based memory: the sneak paths problem and solutions. Microelectronics J. 44(2), 176–183 (2013)

    Article  Google Scholar 

  50. I. Vourkas, D. Stathis and G.C. Sirakoulis, Improved read voltage margins with alternative topologies for memristor-based crossbar memories, in 21st IFIP/IEEE International Conference on on Very Large Scale Integrated (VLSI-SoC), Istanbul (2013)

    Google Scholar 

  51. I. Vourkas, A. Batsos, G.C. Sirakoulis, SPICE modeling of nonlinear memristive behavior. Int. J. Circ. Theor. Appl. 43(5), 553–565 (2015)

    Google Scholar 

  52. I. Vourkas, G.C. Sirakoulis, Employing threshold-based behavior and network dynamics for the creation of memristive logic circuits and architectures. Physica Status Solidi (c), in Proceedings of E-MRS 2014 Spring Meeting Symposium S: Memristor materials, mechanisms and devices for unconventional computing, vol. 12, no. 1-2, pp. 168–174 (2015)

    Google Scholar 

  53. Easy Java Simulations (EJS). Available: http://fem.um.es/Ejs/. Accessed 2014

  54. Y. Ho, G.M. Huang, P. Li, Dynamical properties and design analysis for nonvolatile memristor memories. IEEE Trans. Circuits Syst. I, Reg. Papers 58(4), 724–736 (2011)

    Article  MathSciNet  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece

    Ioannis Vourkas & Georgios Ch. Sirakoulis

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  1. Ioannis Vourkas
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  2. Georgios Ch. Sirakoulis
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Correspondence to Ioannis Vourkas .

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Vourkas, I., Sirakoulis, G.C. (2016). Memristor-Based Logic Circuits. In: Memristor-Based Nanoelectronic Computing Circuits and Architectures. Emergence, Complexity and Computation, vol 19. Springer, Cham. https://doi.org/10.1007/978-3-319-22647-7_4

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  • DOI: https://doi.org/10.1007/978-3-319-22647-7_4

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