Efficient Buffer Management for PCM-Enhanced Hybrid Memory Architecture

Abstract

Recently, phase change memory (PCM) has been considered in memory architecture to serve as an extension to DRAM, due to its special properties of byte-addressibility, low energy consumption, and high read performance. However, PCM has a lower write speed than DRAM. Besides, it has a limited write endurance. Therefore, the co-existence of PCM and DRAM in main memory urges a careful buffer-management policy to avoid frequent writes to PCM. To address this problem, we present the first approach that reduces PCM writes by efficient page exchanges and page replacements. Specially, we propose two clock data structures to maintain DRAM and PCM pages, and devise a page exchange method to make recently-updated pages reside in DRAM. In addition, differing from previous studies that do not consider the influence of page replacements on PCM writes, we present a new page replacement algorithm to reduce page replacement on PCM. With this mechanism, we can reduce PCM writes efficiently while keeping a high hit ratio. We conduct trace-driven experiments on both synthetic and real traces. The experimental results suggest that our proposal can greatly reduce PCM writes and maintain a high hit ratio for PCM/DRAM-based hybrid memory architecture.