Abstract
A method of partial reconfiguration of logic controllers implemented in FPGA is presented in the chapter. Only the control memory content is replaced while the rest of the system is not modified. The logic synthesis and implementation are performed only once. Therefore, such a realisation highly accelerates the whole prototyping process. The performed experiments showed that the original bit-stream that is sent to the FPGA can be reduced even over 500 times.
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Wiśniewski, R., Wiśniewska, M., Adamski, M. (2016). Effective Partial Reconfiguration of Logic Controllers Implemented in FPGA Devices. In: Karatkevich, A., Bukowiec, A., Doligalski, M., Tkacz, J. (eds) Design of Reconfigurable Logic Controllers. Studies in Systems, Decision and Control, vol 45. Springer, Cham. https://doi.org/10.1007/978-3-319-26725-8_4
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