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Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems

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The Dark Side of Silicon

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Abstract

With deeper technology scaling accompanied by a worsening power-wall, an increasing proportion of chip area on a chip multiprocessor (CMP) is expected to be occupied by dark silicon. At the same time, design challenges due to process variations and soft-errors in integrated circuits are projected to become even more severe. It is well known that spatial variations in process parameters introduce significant unpredictability in the performance and power profiles of CMP cores. By mapping applications on to the best set of cores, process variations could potentially be used to our advantage in the dark-silicon era. In addition, the probability of occurrence of soft-errors during execution of any application has been found to be strongly related to the supply voltage and operating frequency values, thus necessitating reliability awareness within run-time voltage scaling schemes in contemporary CMPs. In this chapter, we present a novel framework that leverages the knowledge of variations on the chip to perform run-time application mapping and dynamic voltage scaling (DVS) to optimize system performance and energy, while satisfying dark-silicon power constraints of the chip as well as application-specific performance and reliability constraints. Our experimental results show average savings of 35–80 % in application service times and 13–15 % in energy consumption, compared to prior work.

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Acknowledgements

This research is supported by grants from SRC, NSF (CCF-1252500, CCF-1302693), and AFOSR (FA9550-13-1-0110).

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA

    Nishit Kapadia & Sudeep Pasricha

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  1. Nishit Kapadia
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Correspondence to Nishit Kapadia .

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Editors and Affiliations

  1. University of Turku, Turku, Finland

    Amir M. Rahmani

  2. University of Turku, Turku, Finland

    Pasi Liljeberg

  3. Department of Electronic systems, School of ICT, KTH, Royal Institute of Technology, Kista, Sweden

    Ahmed Hemani

  4. Vienna University of Technology, Vienna, Austria

    Axel Jantsch

  5. KTH Royal Institute of Technology, Stockholm, Sweden

    Hannu Tenhunen

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Kapadia, N., Pasricha, S. (2017). Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems. In: Rahmani, A., Liljeberg, P., Hemani, A., Jantsch, A., Tenhunen, H. (eds) The Dark Side of Silicon. Springer, Cham. https://doi.org/10.1007/978-3-319-31596-6_8

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  • DOI: https://doi.org/10.1007/978-3-319-31596-6_8

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