Abstract
A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-Level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain-Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this chapter we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been designed focusing on the development of FPGA-based, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.
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Notes
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Freely available in http://www.eda.org/fphdl/.
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Acknowledgements
The authors would like to thank FAPESP (the Foundation to Support Research of the State of São Paulo) for the financial support provided.
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de Oliveira, C.B., Menotti, R., Cardoso, J.M.P., Marques, E. (2016). A Special-Purpose Language for Implementing Pipelined FPGA-Based Accelerators. In: Drechsler, R., Wille, R. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 385. Springer, Cham. https://doi.org/10.1007/978-3-319-31723-6_4
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