Abstract
We present a practical and highly secure method for the authentication of chips based on a new concept for implementing strong Physical Unclonable Function (PUF) on field programmable gate arrays (FPGA). Its qualitatively novel feature is a remote reconfiguration in which the delay stages of the PUF are arranged to a random pattern within a subset of the FPGA’s gates. Before the reconfiguration is performed during authentication the PUF simply does not exist. Hence even if an attacker has the chip under control previously she can gain no useful information about the PUF. This feature, together with a strict renunciation of any error correction and challenge selection criteria that depend on individual properties of the PUF that goes into the field make our strong PUF construction immune to all machine learning attacks presented in the literature. More sophisticated attacks on our strong-PUF construction will be difficult, because they require the attacker to learn or directly measure the properties of the complete FPGA. A fully functional reference implementation for a secure “chip biometrics” is presented. We remotely configure ten 64-stage arbiter PUFs out of 1428 lookup tables within a time of 25 s and then receive one “fingerprint” from each PUF within 1 ms.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Below “chip” will be a shorthand our FPGA and “PUF” for one instance of our arbiter PUF construction.
- 2.
The upper limit has no units because one cannot measure the absolute delay times with machine learning programs.
- 3.
The SmartFusion2 chip does not support a partial reconfiguration of the FPGA.
- 4.
With JTAG programming the total programming cycle took 25 s.
- 5.
We will argue below (Sect. 5) that the difficulty of understanding the routing enhances the security of our design by obfuscation.
- 6.
Therefore our PUF construction has 0.0072 \(\times \) 2\(^{64}\) = 1.3 \(\times \) 10\(^{17}\) m-challenges.
- 7.
Here we define the bias as \({(\# \mathrm{\ of \ ones}) - (\# \mathrm{\ of \ zeros}) \over (\# \mathrm{\ of \ ones}) + (\# \mathrm{\ of \ zeros})}\).
References
Becker, G.T.: On the pitfalls of using arbiter PUFs as building blocks. IEEE Trans. Inf. Forensics Secur. 34, 1295–1307 (2015)
Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Delay-based circuit authentication and applications. In: Proceedings of the 18th Annual ACM Symposium on Applied Computing, pp. 294–301. ACM Digital Library, March 2003
Gehrer, S., Sigl, G.: Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation. J. Circ. Syst. Comput. 25(01), 1640002 (2016)
Katzenbeisser, S., Kocabas, Ü., van der Leest, V., Sadeghi, A., Schrijen, G., Schröder, H., Wachsmann, C.: Recyclable PUFs: logically reconfigurable PUFs. J. Crypt. Eng. 1, 177 (2011)
Lao, Y., Parhi, K.: Novel reconfigurable silicon physical unclonable functions. In: Proceedings of Workshop on Foundations of Dependable and Secure Cyber-Physical Systems (FDSCPS), pp. 30–36 (2011)
Killmann, W., Schindler, W.: A proposal for: functionality classes for random number generators (2011). https://www.bsi.bund.de/SharedDocs/Downloads/DE/BSI/Zertifizierung/Interpretationen/AIS_20_Functionality_classes_for_random_number_generators_e.html
Machida, T., Yamamoto, D., Iwamoto, M., Sakiyama, K.: A new mode of operation for arbiter PUF to improve uniqueness on FPGA. In: Proceedings of Federated Conference on Computer Science and Information Systems (FedCSIS), pp. 871–878. IEEE Press, New York (2014)
Maes, R.: Physically unclonable functions: constructions, properties and applications. Ph.D. thesis, Katholieke Universiteit Leuven (2012)
Majzoobi, M., Koushanfar, F., Potkonjak, M.: Techniques for design and implementation of secure reconfigurable PUFs. ACM Trans. Reconfigurable Technol. Syst. 2, 5 (2009)
Majzoobi, M., Koushanfar, F., Devadas, S.: FPGA PUF using programmable delay lines. In: Information Forensics and Security (WIFS), pp. 1–6. IEEE Press, New York (2010)
Majzoobi, M., Kharaya, A., Koushanfar, F., Devadas, S.: Automated design, implementation, and evaluation of arbiter-based PUF on FPGA using programmable delay lines (2014). http://eprint.iacr.org/2014/639.pdf
Microsemi Corporation SmartFusion2 System-on-Chip FPGAs Product Brief (2013). http://www.actel.com/documents/SmartFusion2_DS.pdf
Morozov, S., Maiti, A., Schaumont, P.: An analysis of delay based PUF implementations on FPGA. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds.) ARC 2010. LNCS, vol. 5992, pp. 382–387. Springer, Heidelberg (2010)
Pappu, R.: Physical one-way functions. Ph.D. thesis, MIT (2001). Pappu, R., Recht, B., Taylor, J., Gershenfeld, N.: Physical one-way functions. Science 297, 2026–2030 (2002)
Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling attacks on physical unclonable functions. In: ACM Conference on Computer and Communications Security (CCS), pp. 237–249 (2010)
Rührmair, U., Sölter, J., Sehnke, F., Xu, X., Mahmoud, A., Stoyanova, V., Dror, G., Schmidhuber, J., Burleson, W., Devadas, S.: PUF modeling attacks on simulated and silicon data. IEEE Trans. Inf. Forensics Secur. 8, 1876–1891 (2013)
Rührmair, U.: Disorder-based security hardware: an overview. In: Chang, C., Potkonjak, M. (eds.) Security System Design and Trustable Computing, pp. 3–37. Springer, Cham (2016)
Tajik, S., Dietz, E., Frohmann, S., Dittrich, H., Nedospasov, D., Helfmeier, C., Seifert, J., Boit, C., Hübers, H.: A complete and linear physical characterization methodology for the arbiter PUFFamily (2015). https://eprint.iacr.org/2015/871
Tarnovsky, C.: Deconstructing a “secure” processor. In: Black Hat Federal 2010, Washington (2010). https://www.blackhat.com/presentations/bh-dc-10/Tarnovsky_Chris/BlackHat-DC-2010-Tarnovsky-DASP-slides.pdf
Tobisch, J., Becker, G.: On the scaling of machine learning attacks on PUFs with application to noise bifurcation. In: Schaumont, P., Mangard, S. (eds.) RFIDsec 2015. LNCS, vol. 9440, pp. 17–31. Springer, Heidelberg (2015). doi:10.1007/978-3-319-24837-0_2
Xu, T., Potkonjak, M.: Digital bimodal functions and digital physical unclonable functions: architecture and applications. In: Chang, C., Potkonjak, M. (eds.) Security System Design and Trustable Computing, pp. 83–113. Springer, Cham (2016)
Zalikava, S.S., Zhang, L., Klybik, V.P., Ivaniuk, A.A., Chang, C.: Design and implementation of high-quality physical unclonable functions for hardware-oriented cryptography. In: Chang, C., Potkonjak, M. (eds.) Security System Design and Trustable Computing, pp. 39–81. Springer, Cham (2016)
Zhang, J., Lin, Y.: Reconfigurable binding against FPGA replay attacks. ACM Trans. Des. Autom. Electron. Syst. 20, 33 (2015)
Acknowledgements
We thank Georg Becker, Shahin Tajic, Jean-Pierre Seifert and Marco Winzker for helpful discussions. Georg Becker kindly provided a copy of his machine-learning program to us.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Appendix
Appendix
VHDL Code for our arbiter PUF construction. “above” and “below” stand for the upper and lower signal pathes. [...] stands for the insertion of 62 additional consecutive, identical sub-parts of the code.
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Spenke, A., Breithaupt, R., Plaga, R. (2016). An Arbiter PUF Secured by Remote Random Reconfigurations of an FPGA. In: Franz, M., Papadimitratos, P. (eds) Trust and Trustworthy Computing. Trust 2016. Lecture Notes in Computer Science(), vol 9824. Springer, Cham. https://doi.org/10.1007/978-3-319-45572-3_8
Download citation
DOI: https://doi.org/10.1007/978-3-319-45572-3_8
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-45571-6
Online ISBN: 978-3-319-45572-3
eBook Packages: Computer ScienceComputer Science (R0)