Abstract
Keeping compute and I/O performance balanced is a major challenge for future cost-efficient HPC systems. Several architectural concepts and new technologies allow to address this challenge, however at the price of higher complexity. In this paper we propose a particular approach to exploring the design space using event simulation models that take I/O server-side performance counters as input. In this way real-life data can be used to explore architectural modifications. We apply our approach using data collected by a GPFS file system serving a petascale Blue Gene/P installation.
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Acknowledgments
This work has been performed in the context of the Exascale Innovation Center at Jülich Supercomputing Center. It was partially funded by the state of North Rhine-Westfalia (“Anschubfinanzierung zum Aufbau des Exascale Innovation Center (EIC)”). We acknowledge furthermore the help of Wolfgang Frings, Michael Hennecke and Willi Homberg for collecting and managing JUGENE’s I/O performance data.
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El Sayed, S., Bolten, M., Pleiter, D. (2016). Parallel I/O Architecture Modelling Based on File System Counters. In: Taufer, M., Mohr, B., Kunkel, J. (eds) High Performance Computing. ISC High Performance 2016. Lecture Notes in Computer Science(), vol 9945. Springer, Cham. https://doi.org/10.1007/978-3-319-46079-6_43
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DOI: https://doi.org/10.1007/978-3-319-46079-6_43
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