Functional Verification of AMS-SoC Models Using Hardware Emulation Platforms

Abstract

SystemC-AMS extensions to SystemC have been used in several applications to model the analog part of a heterogeneous SoC. The SoC is usually a pure simulation model where the digital part is modeled using SystemC. If an emulation verification environment is used, the digital part of the SoC would be running on the emulator while the analog part, modeled with SystemC-AMS, would be running on the co-model machine connected to emulator. In this paper, we propose an approach to interface SystemC-AMS models running on the emulator co-model machine with digital models running on the emulator. The verification challenge, addressed by this approach, lies in the fact that execution semantics of models running on the co-model machine connected to the emulator are inherently untimed, and SystemC-AMS is a timed environment with a time wheel completely independent from the emulation time wheel. Our approach presents execution dynamics to address this problem. We also describe a case study that demonstrates the validity of the proposed approach.