Abstract
This chapter will discuss the overall design verification (DV) challenges and solutions. Why is DV still such a long pole in the design cycle? We will discuss a comprehensive verification plan and see the type of expertise required at each step of verification and how to improve the develop => simulate => debug => cover loop.
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Mehta, A.B. (2018). Functional Verification: Challenges and Solutions. In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_2
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DOI: https://doi.org/10.1007/978-3-319-59418-7_2
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-59417-0
Online ISBN: 978-3-319-59418-7
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