Abstract
In the Cloud Radio Access Network (C-RAN), the Software Defined Radio (SDR) is combined with multi-mode base stations (BSs) together. A lot of BSs are centralized in a Cloud center, the centralized BSs need high bandwidth and cost-effective resource allocation. Since BSs may also run on the virtualized machines, the hardware accelerator can provide faster signal processing speed. This paper uses the Xen virtualization to set up a C-RAN platform, where the SDR and the FPGA hardware connected with PCIe interface to server as the signal processing hardware accelerator. Experimental results demonstrate the turbo decoder accelerator based on the FPGA and Xen platform has good performance to support the SDR signal processing with high bandwidth. The turbo decoder hardware accelerator solved the timing constraints in C-RAN.
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Acknowledgments
This work was supported in part by National Science and Technology Major Project of China under Grant 2014ZX03003003, in part by the National Natural Science Foundation of China under Grant 61390513.
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© 2018 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Tang, S., Zhang, Z., Wu, J., Zhu, H. (2018). FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access Network (C-RAN). In: Chen, Q., Meng, W., Zhao, L. (eds) Communications and Networking. ChinaCom 2016. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 209. Springer, Cham. https://doi.org/10.1007/978-3-319-66625-9_21
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DOI: https://doi.org/10.1007/978-3-319-66625-9_21
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