Abstract
Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) containing programmable logic components that can be reconfigured by an end-user post manufacturing. Similar to ICs, FPGAs are also susceptible to supply-chain attacks, especially insertion of hardware Trojans. In this book chapter, we explain how attackers can insert Trojans into FPGAs. We present a Trojan taxonomy that is tailored to FPGA supply chain. We then discuss the main classes of Trojans in FPGAs and explain the different ways of inserting these Trojans in detail. Finally, we present the various countermeasures that have been developed to target Trojans that are FPGA specific.
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Notes
- 1.
Translate and map processes are the terms used by Xilinx, an FPGA vendor. These processes may use different names/terms.
References
S. Adee, The hunt for the kill switch (2008), http://spectrum.ieee.org/semiconductors/design/the-hunt-for-the-kill-switch. Last accessed 13 July 2016
A. Agarwal, D. Blaauw, V. Zolotov, Statistical timing analysis for intra-die process variations with spatial correlations, in IEEE International Conference on Computer Design (2003), pp. 900–907
Amazon, Amazon EC2 F1 instances – run custom FPGAs in the AWS cloud, https://aws.amazon.com/ec2/instance-types/f1/. Last accessed 12 May 2017
A. Amouri, M. Tahoori, High-level aging estimation for FPGA-mapped designs, in IEEE International Conference on Field-Programmable Logic and Applications (2012), pp. 284–291
G.T. Becker, F. Regazzoni, C. Paar, W.P. Burleson, Stealthy dopant-level hardware trojans, in International Workshop on Cryptographic Hardware and Embedded Systems (2013), pp. 197–214
K. Bernstein, D.J. Frank, A.E. Gattiker, W. Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak, D.J. Pearson, N.J. Rohrer, High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50, 433–449 (2006)
A. Bravaix, C. Guerin, V. Huard, D. Roy, J. Roux, E. Vincent, Hot-carrier acceleration factors for low power management in DC-AC stressed 40 nm NMOS node at high temperature, in IEEE International Reliability Physics Symposium (2009), pp. 531–548
D. Bryan, The ISCAS85 benchmark circuits and netlist format. North Carolina State University, 25 (1985)
A.N. Campbell, K.A. Peterson, D.M. Fleetwood, J.M. Soden, Effects of focused ion beam irradiation on MOS transistors, in IEEE International Reliability Physics Symposium (1997), pp. 72–81
R.S. Chakraborty, I. Saha, A. Palchaudhuri, G.K. Naik, Hardware Trojan insertion by direct modification of FPGA configuration bitstream, in IEEE Design & Test (2013), pp. 45–54
H. Chang, S.S. Sapatnekar, Statistical timing analysis under spatial correlations, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2005), pp. 1467–1482
B. Cline, K. Chopra, D. Blaauw, Y. Cao, Analysis and modeling of CD variation for statistical static timing, in IEEE International Conference on Computer Design (2006), pp. 60–66
DARPA, Defense Science Board (DSB) study on high performance microchip supply (2005). http://www.acq.osd.mil/dsb/reports/ADA435563.pdf. Last accessed 13 July 2016
Defense Tech, Proof that military chips from China are infected? (2012). http://www.defensetech.org/2012/05/30/smoking-gun-proof-that-military-chips-from-china-are-infected/. Last accessed 13 July 2016
EETimes, Report: Bogus U.S. military parts traced to China (2011). http://www.eetimes.com/document.asp?doc_id=1125076. Last accessed 13 July 2016
V. Huard, M. Denais, C. Parthasarathy, NBTI degradation: from physical mechanisms to modelling. Microelectron. Reliab. 46, 1–23 (2006)
Intelligence Advanced Research Projects Activity, Trusted integrated circuits program. https://www.fbo.gov/utils/view?id=b8be3d2c5d5babbdffc6975c370247a6. Last accessed 13 July 2016
V. Jyothi, M. Thoonoli, R. Stern, R. Karri, FPGA trust zone: incorporating trust and reliability into FPGA designs, in IEEE International Conference on Computer Design (2016), pp. 600–605
R. Karri, J. Rajendran, K. Rosenfeld, M. Tehranipoor, Trustworthy hardware: identifying and classifying hardware trojans. Computer 43, 39–46 (2010)
P. Lysaght, B. Blodget, J. Mason, J. Young, B. Bridgford, Invited paper: enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs, in IEEE International Conference on Field Programmable Logic and Applications (2006), pp. 1–6
S. Mal-Sarkar, A. Krishna, A. Ghosh, S. Bhunia, Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures, in ACM Great Lakes Symposium on VLSI Design (2014), pp. 287–292
A. Moradi, A. Barenghi, T. Kasper, C. Paar, On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from Xilinx Virtex-II FPGAs, in ACM conference on Computer and Communications Security (2011), pp. 111–124
C.J. Morford, Bitmat-bitstream manipulation tool for Xilinx FPGAs. PhD dissertation, Virginia Tech (2005). https://theses.lib.vt.edu/theses/available/etd-12162005-144728/unrestricted/CMorford_Thesis.pdf. Last accessed 22 May 2017
J.-B. Note, É. Rannaud, From the bitstream to the netlist, in International ACM/SIGDA Symposium on Field Programmable Gate Arrays (2008), vol. 8, pp. 264–264
Y. Pino, V. Jyothi, M. French, Intra-die process variation aware anomaly detection in FPGAs, in IEEE International Test Conference (2014), pp. 1–6
J. Rajendran, V. Jyothi, O. Sinanoglu, R. Karri, Design and analysis of ring oscillator based design-for-trust technique, in IEEE VLSI Test Symposium (2011), pp. 105–110
J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Logic encryption: a fault analysis perspective, in Design, Automation Test in Europe Conference Exhibition (2012), pp. 953–958
J. Rajendran, H. Zhang, O. Sinanoglu, R. Karri, High-level synthesis for security and trust, in IEEE International On-Line Testing Symposium (2013), pp. 232–233
J. Rajendran, O. Sinanoglu, R. Karri, Building trustworthy systems using untrusted components: a high-level synthesis approach. IEEE Trans. Very Large Scale Integr. Syst. 24(9), 2946–2959 (2016)
SEMI, Innovation is at risk as semiconductor equipment and materials industry loses up to $4 billion annually due to IP infringement (2008). www.semi.org/en/Press/P043775. Last accessed 13 July 2015
Y. Shiyanovskii, F. Wolff, A. Rajendran, C. Papachristou, D. Weyer, W. Clay, Process reliability based Trojans through NBTI and HCI effects, in NASA/ESA Conference on Adaptive Hardware and Systems (2010), pp. 215–222
S.P. Skorobogatov, R.J. Anderson, Optical fault induction attacks, in International Workshop on Cryptographic Hardware and Embedded Systems (2002), pp. 2–12
P. Swierczynski, M. Fyrbiak, P. Koppe, C. Paar, FPGA Trojans through detecting and weakening of cryptographic primitives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34, 1236–1249 (2015)
M. Tehranipoor, F. Koushanfar, A survey of hardware Trojan taxonomy and detection. IEEE Des. Test Comput. 27, 10–25 (2010)
R. Torrance, D. James, The state-of-the-art in semiconductor reverse engineering, in IEEE/ACM Design Automation Conference (2011), pp. 333–338
Transparency Market Research, FPGA market – Global industry analysis, size, share, growth, trends and forecast, 2014–2020. http://www.transparencymarketresearch.com/field-programmable-gate-array.html. Last accessed 22 May 2017
USPTO, Piracy of intellectual property (2005). http://www.uspto.gov/about-us/news-updates/piracy-intellectual-property. Last accessed 13 July 2016
Xilinx, Virtex-II platform FPGA user guide (v 2.2). www.xilinx.com/support/documentation/user_guides/ug002.pdf. Last accessed 22 May 2017
X. Zhang, M. Tehranipoor, RON: an on-chip ring oscillator network for hardware Trojan detection, in IEEE Design, Automation Test in Europe Conference Exhibition (2011), pp. 1–6
W. Zhang, K. Balakrishnan, X. Li, D.S. Boning, S. Saxena, A. Strojwas, R. Rutenbar, Efficient spatial pattern analysis for variation decomposition via robust sparse regression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32, 1072–1085 (2013)
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Jyothi, V., Rajendran, J.(. (2018). Hardware Trojan Attacks in FPGA and Protection Approaches. In: Bhunia, S., Tehranipoor, M. (eds) The Hardware Trojan War. Springer, Cham. https://doi.org/10.1007/978-3-319-68511-3_14
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DOI: https://doi.org/10.1007/978-3-319-68511-3_14
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