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Architecture Level Optimizations for Kummer Based HECC on FPGAs

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Progress in Cryptology – INDOCRYPT 2017 (INDOCRYPT 2017)

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Abstract

On the basis of a software implementation of Kummer based HECC over \(\mathbb {F}_p\) presented in 2016, we propose new hardware architectures. Our main objectives are: definition of architecture parameters (type, size and number of units for arithmetic operations, memory and internal communications); architecture style optimization to exploit internal parallelism. Several architectures have been designed and implemented on FPGAs for scalar multiplication acceleration in embedded systems. Our results show significant area reduction for similar computation time than best state of the art hardware implementations of curve based solutions.

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Notes

  1. 1.

    Our CCABA model is inspired by Transaction Level Modeling (TLM) with full cycle accuracy for all control signals at the architecture level but not inside the units (when there is no input/output impact).

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Acknowledgment

This work was done in the HAH project http://h-a-h.inria.fr/ partially funded by Labex CominLab, Labex Lebesgue and Brittany Region.

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Correspondence to Arnaud Tisserand .

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Gallin, G., Celik, T.O., Tisserand, A. (2017). Architecture Level Optimizations for Kummer Based HECC on FPGAs. In: Patra, A., Smart, N. (eds) Progress in Cryptology – INDOCRYPT 2017. INDOCRYPT 2017. Lecture Notes in Computer Science(), vol 10698. Springer, Cham. https://doi.org/10.1007/978-3-319-71667-1_3

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  • DOI: https://doi.org/10.1007/978-3-319-71667-1_3

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