Abstract
This chapter discusses the validation of the EPFL substrate model against experimental data of parasitic couplings measured from specific test circuits fabricated in a HV-CMOS technology. The substrate model is based on a distributed network composed of three lumped components whose parameters must be calibrated. Therefore, a specific technology calibration methodology is developed and uses the electrical characteristics of simple structures such as diodes and bipolar transistors. Parasitic simulations are compared with measurements of substrate couplings in simple test structures, in a high-voltage H-Bridge, and in a rotor coil driver used in automotive alternators. The results are also discussed in terms of computational resources needed for the extraction and simulation of the substrate model.
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Buccella, P., Stefanucci, C., Kayal, M., Sallese, JM. (2018). Parasitic Bipolar Transistors in Benchmark Structures. In: Parasitic Substrate Coupling in High Voltage Integrated Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-74382-0_6
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DOI: https://doi.org/10.1007/978-3-319-74382-0_6
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