Skip to main content
SpringerLink
Log in

MASH 2-2 CTΔΣM with Fully Integrated Quantization Noise Leakage Calibration

  • Chapter
  • First Online:
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators

  • 757 Accesses

Abstract

This chapter presents a MASH 2-2 CTΔΣM with on-chip RC time-constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise cancelation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CTΔΣM stages, each of which consists of an integrator-based active-RC loop filter, current-steering feedback digital-to-analog converters, and a four-bit Flash quantizer. On-chip RC time-constant calibration circuits and high-gain multi-stage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to (1) synthesize a fourth-order noise transfer function with DC zeros, (2) simplify the design of NCF, and (3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40 nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise and distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power (P) from 1.1, 1.15, and 2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function (STF) peaking.

This Chap. 6 includes portions reprinted with permission from A. Edward, Q. Liu, C. Briseno-Vidrios, M. Kinyua, E. G. Soenen, A. I. Karsilayan, and J. Silva-Martinez.: A 43-mW MASH 2-2 CT ΔΣ modulator attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid-State Circuits (JSSC) 52(2), 448–459 (2017), Ⓒ2017 IEEE

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. N. Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, H. Arora, S. Uppathil, S. Kaylor, A. Akour, V. Wang, M. Mares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, C. Sestok, C. Fernando, K. Rajagopal, S. Ramakhrisnan, V. Sinari, V. Baireddy, A 45nm CMOS RF-to-bits LTE/WCDMA FDD/TDD 2x2 MIMO base-station transceiver SoC with 200 MHz RF bandwidth, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2016), pp. 164–165

    Google Scholar 

  2. M. Bolatkale, L.J. Breems, R. Rutten, K.A.A. Makinwa, A 4 Ghz continuous-time ΔΣ ADC with 70 dB DR and -74 dBFS THD in 125 MHz BW. IEEE J. Solid State Circuits 46(12), 2857–2867 (2011)

    Article  Google Scholar 

  3. P. Shettigar, S. Pavan, Design techniques for wideband single-bit continuous-time ΔΣ modulators with FIR feedback DACs. IEEE J. Solid State Circuits 47(12), 2865–2879 (2012)

    Article  Google Scholar 

  4. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth. IEEE J. Solid State Circuits 41(12), 2641–2649 (2006)

    Article  Google Scholar 

  5. V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, M. Corsi, A 20mW 61dB SNDR (60 MHz BW) 1b 3rd-Order continuous-time delta-sigma modulator clocked at 6 GHz in 45 nm CMOS, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2012), pp. 158–159

    Google Scholar 

  6. T. Caldwell, D. Alldred, Z. Lai, A reconfigurable ΔΣ ADC with up to 100 MHz bandwidth using flash reference shuffling. IEEE Trans. Circuits Syst. I 61(8), 2263–2271 (2014)

    Article  Google Scholar 

  7. J.G. Kauffman, C. Chu, J. Becker, M. Ortmanns, A 67 dB DR 50 MHz BW CT Delta Sigma modulator achieving 207 fJ/conv, in IEEE Asian Solid-State Circuits Conference (ASSCC) Dig. Tech. Papers, Singapore (2013), pp. 401–404

    Google Scholar 

  8. S. Ho, C-L. Lo, J. Ru, J. Zhao, A 23 mW, 73 dB dynamic range, 80 MHz BW continuous-time delta-sigma modulator in 20 nm CMOS. IEEE J. Solid State Circuits 50(4), 908–919 (2015)

    Article  Google Scholar 

  9. B. Young, K. Reddy, S. Rao, A. Elshazly, T. Anand, P.K. Hanumolu, A 75dB DR 50 MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Honolulu (2014), pp. 1–2

    Google Scholar 

  10. C. Briseno-Vidrios, A. Edward, A. Shafik, S. Palermo, J. Silva-Martinez, ‘A 75 MHz BW 68dB DR CT-ΣΔ with single amplifier biquad filter and a broadband low-power common-gate summing technique, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Kyoto (2015), pp. C254–C255

    Google Scholar 

  11. S. Loeda, J. Harrison, F. Pourchet, A. Adams, A 10/20/30/40 MHz feedforward FIR DAC continuous-time ΔΣ ADC with robust blocker performance for radio receivers. IEEE J. Solid State Circuits 51(4), 860–870 (2016)

    Article  Google Scholar 

  12. K. Reddy, S. Dey, S. Rao, B. Young, P. Prabha, P.K. Hanumolu, ‘A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Kyoto (2015), pp. C256–C257

    Google Scholar 

  13. S.-H. Wu, T.-K. Kao, Z.-M. Lee, J.-Y. Tsai, A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2016), pp. 280–281

    Google Scholar 

  14. A. Jain, S. Pavan, ‘A 13.3mW 60MHz bandwidth, 76dB DR 6GS/s CTDSM with time interleaved FIR feedback, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Honolulu (2016), pp. 1–2

    Google Scholar 

  15. L.J. Breems, R. Rutten, G. Wetzker, A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth. IEEE J. Solid State Circuits 39(12), 2152–2160 (2004)

    Article  Google Scholar 

  16. L.J. Breems, R. Rutten, R.H.M. van Veldhoven, G. van der Weide, A 56 mW continuous-time quadrature cascaded ΣΔ modulator with 77 dB DR in a near zero-IF 20 MHz band. IEEE J. Solid State Circuits 42(12), 2696–2705 (2007)

    Article  Google Scholar 

  17. Y.-S. Shu, J. Kamiishi, K. Tomioka, K. Hamashita, B.-S. Song, LMS-based noise leakage calibration of cascaded continuous-time ΔΣ modulators. IEEE J. Solid State Circuits 45(2), 368–379 (2010)

    Article  Google Scholar 

  18. J. Sauerbrey, J.S.P. Garcia, G. Panov, T. Piorek, X. Shen, M. Schimper, R. Koch, M. Keller, Y. Manoli, M. Ortmanns, G. Gielen, ‘A configurable cascaded continuous-time ΔΣ modulator with up to 15 MHz bandwidth, in IEEE European Solid-State Circuits Conference (ESSCIRC) Dig. Tech. Papers, Sevilla (2010), pp. 426–429

    Google Scholar 

  19. Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami, S. Korrapati, A continuous-time 0-3 MASH ADC achieving 88 dB DR with 53 MHz BW in 28 nm CMOS. IEEE J. Solid State Circuits 49(12), 2868–2877 (2014)

    Article  Google Scholar 

  20. D.-Y. Yoon, S. Ho, H.-S. Lee, A continuous-time Sturdy-MASH ΔΣ modulator in 28 nm CMOS. IEEE J. Solid State Circuits 50(12), 2880–2890 (2015)

    Article  Google Scholar 

  21. Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata, R. Schreier, Q. Meng, J. Silva, D. Paterson, J. Gealow, A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2016), pp. 278–279

    Google Scholar 

  22. B. Nowacki, N. Paulino, J. Goes, A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2016), pp. 274–275

    Google Scholar 

  23. N. Maghari, S. Kwon, U.-K. Moon, 74 dB SNDR multi-loop Sturdy-MASH delta-sigma modulator using 35 dB open-loop opamp gain. IEEE J. Solid State Circuits 44(8), 2212–2221 (2009)

    Article  Google Scholar 

  24. M. Ortmanns, F. Gerfers, Y. Manoli, A case study on a 2-1-1 cascaded continuous-time sigma-delta modulator. IEEE Trans. Circuits Syst. I 52(8), 1515–1525 (2005)

    Article  MATH  Google Scholar 

  25. B. K. Thandri, Silva-Martinez, A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no miller capacitors. IEEE J. Solid State Circuits 38(2), 237–243 (2003)

    Google Scholar 

  26. T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, A current-controlled latch sense amplifier and a static power-saving input buffer for low power architecture. IEEE J. Solid State Circuits 28(4), 523–527 (1993)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Qualcomm Incorporated, Tempe, AZ, USA

    Qiyuan Liu

  2. Intel Corporation, Hillsboro, OR, USA

    Alexander Edward

  3. Silicon Laboratories Incorporated, Austin, TX, USA

    Carlos Briseno-Vidrios

  4. Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA

    Jose Silva-Martinez

Authors
  1. Qiyuan Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Alexander Edward
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Carlos Briseno-Vidrios
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jose Silva-Martinez
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Liu, Q., Edward, A., Briseno-Vidrios, C., Silva-Martinez, J. (2018). MASH 2-2 CTΔΣM with Fully Integrated Quantization Noise Leakage Calibration. In: Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, Cham. https://doi.org/10.1007/978-3-319-77225-7_6

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-77225-7_6

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-77224-0

  • Online ISBN: 978-3-319-77225-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation