Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors

Abstract

The focus of this work lies on Xilinx’s SRAM-based FPGAs and All Programmable System-on-Chip (AP-SoC) devices that combines FPGAs and ARM processors having the AMBA Advanced eXtensible Interface (AXI) as one of its main interfaces. The use of commercial off-the-shelf SRAM-based FPGA devices integrating multi-core processors and custom IP blocks through general purpose interfaces can help in coping with performance requirements and time-to-market constraints. On the other hand, when considering its application in critical cyberphysical systems, there are reliability issues that must be dealt with. SRAM-based FPGAs are susceptible to soft-errors causing persistent changes on configuration memory that will accumulate until reconfiguration is performed. Mitigation techniques inside the user-designed IP blocks allow to delay this reconfiguration but choices on the interface between those blocks have impact on the effectiveness of the mitigations. This work consisted in evaluating an IP block generated by Xilinx’s High-level Synthesis (HLS) tools and designed to use the AXI Streaming interface available. The results obtained from fault injection allowed to evaluate separately the reliability of the IP block core and the IP block AXI interface showing that, in this case, the IP block interface can undermine the efforts placed in the IP core hardening.