Abstract
Coarse Grained Reconfigurable Architectures (CGRA) have been widely used with General Purpose Processors (GPP) to boost performance of applications by exploiting Instruction Level Parallelism. However, to sustain high performance levels, a great number of functional units must be available, which results in long contexts to represent each configuration. Most CGRA employ dedicated memory structures to store such contexts, in which the memory port width is proportional to the context length. This reduces the reconfiguration time but increases energy consumption. In this work, we propose a Partial Reconfiguration (PR) Technique that focuses on decreasing the energy consumption by storing CGRA contexts in the GPP cache memory hierarchy. This is done by splitting each context into multiple parts (partial contexts), which have the same size as the cache memory block width. Results show that the proposed strategy maintains the performance of the original approach providing, on average, 29 times of energy savings.
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de Moura, R.F., Jordan, M.G., Beck, A.C.S., Rutzig, M.B. (2018). Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_29
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DOI: https://doi.org/10.1007/978-3-319-78890-6_29
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