Selection of Post-Silicon Hardware Assertions

Abstract

Post-silicon validation is an important and time-consuming step in the design flow of system-on-chip (SoC) devices. Electrical errors such as those caused by cross-talk or power droops, are particularly difficult to catch during the pre-silicon phase because of the insufficient accuracy of device models, which is often traded-off against simulation time. These electrically induced subtle errors most commonly manifests in the logic domain as bit-flips in flip-flops. Unlike pre-silicon verification, limited internal node observability is one of the main challenges in post-silicon validation because it causes long error detection latencies if errors can only be observed at the primary outputs. Recent studies have justified the use of hardware assertions to enhance the internal observability and reduce error detection latencies. However, to the best of our knowledge, there are no systematic methods for designing embedded hardware monitors for generic logic blocks that can detect bit-flips with low detection latency. In addition to this, unlike pre-silicon verification and manufacturing test that benefits from well-defined and universally accepted coverage metrics, there is no generic metric from which confidence can be implied at the end of post-silicon validation. Toward these goals, we present methodologies and architectures that rely on design invariants (assertions) that are selected based on their potential to detect bit-flips. We also introduce the flip-flop coverage estimate that can be used to assess the quality of the selected assertions.