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Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes

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Field Programmable Logic and Application (FPL 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3203))

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Abstract

In this paper algorithms and architectures for new GF(3m) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components.

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References

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Author information

Authors and Affiliations

  1. Dept. of Electrical and Electronic Engineering, University College Cork, Cork City, Ireland

    Tim Kerins & William Marnane

  2. Dept. of Microelectronic Engineering, University College Cork, Cork City, Ireland

    Emanuel Popovici

Authors
  1. Tim Kerins
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  2. Emanuel Popovici
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  3. William Marnane
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Editor information

Editors and Affiliations

  1. ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  2. University of Paderborn,  

    Marco Platzner

  3. IMEC, Kapeldreef 75, Leuven, Leuven, Belgium

    Serge Vernalde

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© 2004 Springer-Verlag Berlin Heidelberg

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Kerins, T., Popovici, E., Marnane, W. (2004). Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_10

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  • DOI: https://doi.org/10.1007/978-3-540-30117-2_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22989-6

  • Online ISBN: 978-3-540-30117-2

  • eBook Packages: Springer Book Archive

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