Abstract
Adiabatic CMOS circuits reduce the energy consumption by supplying the charge at a rate significantly lower than the inherent RC delay of a gate. However, such a technique inherently trades energy for delay. In this work, we propose to incorporate an adiabatic charge pump to recycle charge for energy reduction. The adiabatic component, charge pump, is placed away from the critical paths. The adiabatic delays are overlapped with the computing path logic delays resulting in no change in the computation speed. One implementation scheme that taps the ground-bound charge in a capacitor (virtual ground) and then uses an adiabatic charge-pump to feed internal virtual Vdd nodes is described. The method has been implemented in DSP computations such as FIR filter, DCT/IDCT filters and FFT filters. Complete design details and performance analysis are presented. Simulation results in SPICE indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 15% with no loss in performance.
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© 2003 Springer-Verlag Berlin Heidelberg
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Manne, V., Tyagi, A. (2003). An Adiabatic Charge Pump Based Charge Recycling Design Style. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_36
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DOI: https://doi.org/10.1007/978-3-540-39762-5_36
Publisher Name: Springer, Berlin, Heidelberg
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