Abstract
This paper presents the implementation of QR Decomposition based Recursive Least Square (QRD-RLS) algorithm on Field Programmable Gate Arrays (FPGA). The design is based on hardware-software co-design. The hardware part consists of a custom peripheral that solves the part of the algorithm with higher computational costs and the software part consists of an embedded soft core processor that manages the control functions and rest of the algorithm. The use of Givens Rotation and Systolic Arrays make this architecture suitable for FPGA implementation. Moreover, the speed and flexibility of FPGAs render them viable for such computationally intensive application. The system has been implemented on Xilinx Spartan 3E FPGA with Microblaze soft core processor using Embedded Development Kit (EDK). The paper also presents the implementation results and their analysis.
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Lodha, N., Rai, N., Dubey, R., Venkataraman, H. (2009). Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor. In: Prasad, S.K., Routray, S., Khurana, R., Sahni, S. (eds) Information Systems, Technology and Management. ICISTM 2009. Communications in Computer and Information Science, vol 31. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00405-6_23
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DOI: https://doi.org/10.1007/978-3-642-00405-6_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00404-9
Online ISBN: 978-3-642-00405-6
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