Abstract
A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.
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© 2009 Springer-Verlag Berlin Heidelberg
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Li, HY., Hwang, WJ., Hsu, CC., Hung, CL. (2009). Efficient K-Means VLSI Architecture for Vector Quantization. In: Salberg, AB., Hardeberg, J.Y., Jenssen, R. (eds) Image Analysis. SCIA 2009. Lecture Notes in Computer Science, vol 5575. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-02230-2_45
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DOI: https://doi.org/10.1007/978-3-642-02230-2_45
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-02229-6
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