Abstract
In this paper, we propose a dual-mode hybrid ARQ scheme for energy efficient on-chip communication, where the type of coding scheme can be dynamically selected based on different noise environments and reliability requirements. In order to reduce codec area overhead, a hardware sharing design method is implemented, resulting in only a minor increase in area costs compared to a single-mode system. For a given reliability requirement, the proposed error control scheme yields up to 35% energy improvement compared to previous solutions and up to 18% energy improvement compared to worst-case noise design method.
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Fu, B., Ampadu, P. (2009). A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects. In: Cheng, M. (eds) Nano-Net. NanoNet 2008. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 3. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-02427-6_15
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DOI: https://doi.org/10.1007/978-3-642-02427-6_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-02426-9
Online ISBN: 978-3-642-02427-6
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