Abstract
With the development of semiconductor technology, the devices integrated in chips are more and more dense. As a result, the delay of circuit has become a bottleneck problem that impact on the efficiency of chip. In this paper, we proposed a new method to optimize the circuit. In the optimization, we added a few random edges in the regular circuit of FPGA chip. The result shows that the average path length of FPGA chip is significantly reduced after the optimization.
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Zhou, Hp., Cai, Sh. (2011). FPGA Chip Optimization Based on Small-World Network Theory. In: Qi, L. (eds) Information and Automation. ISIA 2010. Communications in Computer and Information Science, vol 86. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19853-3_36
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DOI: https://doi.org/10.1007/978-3-642-19853-3_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19852-6
Online ISBN: 978-3-642-19853-3
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