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Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET

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Trends in Network and Communications (WeST 2011, NeCoM 2011, WiMoN 2011)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 197))

Abstract

The linearity and analog performance of a Silicon Double Gate Tunnel Field Effect Transistor (DG-TFET) is investigated and the impact of elevated temperature on the device performance degradation has been studied. The impact on the device performance due to the rise in temperature has also been investigated for the case of Silicon DG-MOSFET and a comparison with DG-TFET is made. The parameters governing the analog performance and linearity has been studied and the impact of a gate stack (GS) architecture has also been investigated for the same.

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Author information

Authors and Affiliations

  1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi, 110 021, India

    Rakhi Narang & Mridula Gupta

  2. Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, 110 015, India

    Manoj Saxena

  3. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Sector-22, Rohini, Delhi, 110 086, India

    R. S. Gupta

Authors
  1. Rakhi Narang
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  2. Manoj Saxena
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  3. R. S. Gupta
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  4. Mridula Gupta
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Editor information

Editors and Affiliations

  1. Southeastern Louisiana University, 70402, Hammond, LA, USA

    David C. Wyld

  2. Chair of Systems and Computer Networks, Wroclaw University of Technology, Wybrzeze Wyspianskiego 27, 50-370, Wroclaw, Poland

    Michal Wozniak

  3. University of Calcutta, Calcutta, India

    Nabendu Chaki

  4. Jackson State University, 39217, Jackson, MS, USA

    Natarajan Meghanathan

  5. Wireilla Net Solutions PTY Ltd, Melbourne, Victoria, Australia

    Dhinaharan Nagamalai

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© 2011 Springer-Verlag Berlin Heidelberg

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Narang, R., Saxena, M., Gupta, R.S., Gupta, M. (2011). Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET. In: Wyld, D.C., Wozniak, M., Chaki, N., Meghanathan, N., Nagamalai, D. (eds) Trends in Network and Communications. WeST NeCoM WiMoN 2011 2011 2011. Communications in Computer and Information Science, vol 197. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22543-7_47

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  • DOI: https://doi.org/10.1007/978-3-642-22543-7_47

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-22542-0

  • Online ISBN: 978-3-642-22543-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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