Abstract
This paper presents a new interworking architecture for a network processor (NP) that is able to process packets from OSI layer 2 (L2) to layer 7 (L7) by combining a conventional NP with a general-purpose processor (GP). In general, most commercially available NPs could not afford to support a variety of network services. This is mainly because the conventional NPs are not able to process L7 packets. Thus, one of the most important requirements for the state-of-the-art NP is the ability to process packets of L2 to L7. To process L7 packets efficiently through both the conventional NP and GP, the proposed interworking architecture uses a deep packet inspector (DPI) and it controls the packet processing flow depending on the OSI layers of packets. Experimental results show that the proposed interworking architecture is not only able to process packets of L2 to L7 but also increase the throughput and load balance of the packet processing in the NP without large hardware overhead when compared with the conventional interworking architecture.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Yusuf, S., Luk, W., Sloman, M., Dulay, N., Lupu, E.C., Brown, G.: Reconfigurable architecture for network flow analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(1), 57–65 (2008)
Peyravian, M., Calvignac, J.: Fundamental architectural considerations for network processors. Computer Networks 41(5), 587–600 (2003)
Forouzan, B.A.: Data Communications and Networking. McGrawHill (2003)
Shi, L., Zhang, Y., Yu, J., Xu, B., Liu, B., Li, J.: On the extreme parallelism inside next-generation network processors. In: 26th IEEE International Conference on Computer Communications, Alaska, USA, pp. 1379–1387 (2007)
Allen, J., et al.: IBM PowerNP network processor: Hardware, software, and applications. IBM Journal of Research and Development 47(2.3), 177–193 (2003)
EZchip Technologies Ltd., NP-1, http://www.ezchip.com/
Adiletta, M., Rosenbluth, M., Bernstein, D., Wolrich, G., Wilkinson, H.: The next generation of Intel IXP network processors. Intel Technology Journal 6(3) (2002)
Coss, M., Sharp, R.: The Network Processor Decision. Bell Labs Technical Journal, 177–189 (2004)
Thiele, L., Chakraborty, S., Gries, M., Künzli, S.: Network Processor Design, Issues and Practices. In: Crowley, P., Franklin, M., Hadimioglu, H., Onufryk, P. (eds.) Design Space Exploration of Network Processor Architectures, vol. 1, pp. 55–89. Morgan Kaufmann Publishers (2002)
Haas, R., et al.: Creating advanced functions on network processors: experience and perspectives. IEEE Network 17(4) (2003)
Liu, T., Sun, Y., Guo, L.: Fast and Memory-Efficient Traffic Classification with Deep Packet Inspection in CMP Architecture. In: IEEE Fifth International Conference on Networking, Architecture and Storage, pp. 208–217 (2010)
Iyer, S., Kompella, R.R., Shelat, A.: ClassiPITM:An Architecture for Fast and Flexible Packet Classification. IEEE/ACM Trans. Networking 15, 33–41 (2001)
Qi, Y., Xu, B., He, F., Yang, B., Yu, J., Li, J.: Towards high-performance flow-level packet processing on multi-core network processors. In: Proc. 3rd ANCS, Orlando, USA, pp. 17–26 (2007)
Choi, J.Y., Han, J.Y., Cho, E.S., Kim, H.C., Kwon, T.K., Choi, Y.H.: Performance Comparison of Content-oriented Networking Alternatives: A Tree versus A Distributed Hash Table. In: IEEE 34th Conference on Local Computer Networks, pp. 253–256 (2009)
Zhang, J., Qian, Z., Shou, G., Hu, Y.: Online Automatic Traffic Classification Architecture in Access Network. In: ICEMI 2009, vol. 3, pp. 24–29 (2009)
Tian, X., Sun, Q., Huang, X., Ma, Y.: A Dynamic Online Traffic Classification Methodology based on Data Stream Mining. In: WRI World Congress on Computer Science and Information Engineering, vol. 1, pp. 298–302 (2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bae, Kr., Ok, SH., Son, HS., Oh, S.Y., Lee, YH., Moon, B. (2011). An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing. In: Kim, Th., et al. Communication and Networking. FGCN 2011. Communications in Computer and Information Science, vol 265. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27192-2_18
Download citation
DOI: https://doi.org/10.1007/978-3-642-27192-2_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-27191-5
Online ISBN: 978-3-642-27192-2
eBook Packages: Computer ScienceComputer Science (R0)