Abstract
A powerful, flexible and machine portable compiler is described which provides both a simulation base and assembly capabilities for microprocessors of arbitrary architecture. The compiler utilises the STAGE 2 macroprocessor and the ISP defining notation and is of particular importance in that it permits a realistic simulation of multiprocessor systems created from microprocessor arrays.
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© 1978 The World Organisation of General Systems and Cybernetics
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Rudall, B.H., Coates, R.F.W., Shepheard, N.T. (1978). A Compiler Technique for Modelling Multiprocessor Systems Utilising Microprocessors of Arbitrary Architecture. In: Rose, J. (eds) Current Topics in Cybernetics and Systems. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-93104-8_81
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DOI: https://doi.org/10.1007/978-3-642-93104-8_81
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-93106-2
Online ISBN: 978-3-642-93104-8
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