Abstract
This paper presents a simulation model for hierarchically structured multiprocessors based on the Futurebus+. The model simulates the behaviour of the buses and caches at the level of individual memory references. These memory references are generated by a set of “stochastical processes” which are based on measured statistics of actual programs. The model is validated with published trace driven simulations of single and two level cache systems.
We have used the model in some experiments to study the performance effects of cache parameters in various multilevel cache hierarchies. We conclude that a two level hierarchy of caches is attractive for those applications that cause a lot of bus traffic. The parallel application of our benchmark, which heavily uses shared data, showed a performance increase of 44% when a flat bus was replaced by a two-level hierarchy. Finally we observed that 99% of the total of bus transactions in all simulations used only 5% of the Futurebus+ cache-coherency protocol. We conclude that many of the optimizations in the protocol only increase complexity without a clear performance benefit.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Archibald and J. Baer, “Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model”, ACM Transactions on Computer Systems, Vol 4, No. 4, November 1986, pp 273–298.
J. Baer and W. Wang, “On the inclusion properties for multi-level cache hierarchies”, Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988, pp 73–80.
H.O. Bugge, E.H. Kristiansen and B.O. Bakka, “Trace-driven simulations for a two-level cache design in open bus systems”, Proceedings of the 17th Annual Int. Symposium on Computer Architecture, 1990, pp 250–259.
S.J. Eggers and R.H. Katz, “Evaluating the performance of four snooping cache coherency protocols”, Proceedings of the 16th Annual International Symposium on Computer Architecture, 1989, pp 2–15.
Futurebus+, Logical Layer Specifications, Draft 8.1, P896. 1 Working Group of the IEEE Computer Society, December 1989.
J.L. Hennessy and D.A. Patterson, “Computer architecture: a quantitative approach”, Morgan Kaufmann Publishers, Palo Alto, California, 1990.
M.D. Hill, “Aspects of Cache Memory and Instruction Buffer Performance”, Ph.D. Thesis, Univ. of California at Berkeley Computer Science Division, Tech. Rep. UCB/CSD 87 /381, November 1987.
H.L. Muller, “Evaluation of a communication architecture by means of simulation”, Proceedings of the PRISMA workshop on Parallel Database Systems, Noordwijk, The Netherlands, September 24–26, 1990.
P. Sweazy and A.J. Smith, “A class of compatible cache consistency protocols and their support by the IEEE Futurebus”, Proceedings of the 13th Annual International Symposium on Computer Architecture, 1986, pp 414–423.
M.K. Vernon, R. Jog and G.S. Sohi, “Performance Analysis of Hierarchical Cache-Consistent Multiprocessors”, Performance evaluation 9, 1989, pp 287–302.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1991 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Langendoen, K.G., Muller, H.L., Hertzberger, L.O. (1991). Evaluation of Futurebus hierarchical caching. In: Aarts, E.H.L., van Leeuwen, J., Rem, M. (eds) Parle ’91 Parallel Architectures and Languages Europe. Lecture Notes in Computer Science, vol 505. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-25209-3_5
Download citation
DOI: https://doi.org/10.1007/978-3-662-25209-3_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-23206-4
Online ISBN: 978-3-662-25209-3
eBook Packages: Springer Book Archive