Abstract
This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a process/device simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented.
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References
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© 1993 Springer-Verlag Wien
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Kuźmicz, W. et al. (1993). Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits. In: Selberherr, S., Stippel, H., Strasser, E. (eds) Simulation of Semiconductor Devices and Processes. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6657-4_8
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DOI: https://doi.org/10.1007/978-3-7091-6657-4_8
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7372-5
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