Abstract
A generic application-independent validation of VLSI design database is presented. The detected violations are independent of the technology or manufacturing process and the verification is not a substitute for conventional Design Rule Checker (DRC) which is heavily process-dependent. The detection processing is done immediately after completing the VLSI graphic database and is based on a polygon-by-polygon analysis. The various violation types are described and the algorithms are demonstrated. The complexity of the algorithms is linear, compare to N*logN complexity in DRC algorithms. The advantages of using the up-front validation, especially when the database is hierarchical, are discussed.
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Reference
Aho AV, Hopcroft EJ, Ullman DJ (1983) Data Structures and Algorithms. Addison-Wesley, Reading Menlo Park London Amsterdam Don Syndey.
Bentley JL, Ottman TA (1979) Algorithms for Reporting and Counting Geometric Intersections. IEEE Trans. Comp. 6–28(9): 643–647.
Lauther U (1981) An O (N log N) Algorithm For Boolean Mask Operations. Proc. 18th DA Conf., pp. 555–562.
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© 1986 Springer-Verlag Tokyo
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Shiran, Y. (1986). Efficient Algorithms for Validating VLSI Design Database. In: Kunii, T.L. (eds) Advanced Computer Graphics. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68036-9_27
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DOI: https://doi.org/10.1007/978-4-431-68036-9_27
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68038-3
Online ISBN: 978-4-431-68036-9
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