Abstract
“All our dreams can’t be translated into reality. But they can act as foundation stone for our glorious future”
As the technology of communication and storage improves, it needs high security and performance in both software & hardware. This paper describes the design of effective security system for implementing it to encrypt or decrypt the data in storage device. In this paper we are using O’Driocells matrix for mapping & inverse mapping that is used in S-Box calculation which reduces the total no of 1’s to 51 which is less than previously published paper[5] and Mixcolumn is implemented using Combinational logic method instead of Xtime look up table[LUT]. Hence it is effective in terms of speed, low power and high performance. We proposed pipelined AES architecture that can offer low power and high throughput to increase the efficiency.
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References
Daemen, J., Rijmen, V.: AES Proposal: Rijndael (Version 2). NIST AES, http://csrc.nist.gov/publications/ , http://csrc.nist.gov/CryptoToolkit/aes/rijndaellRijndaelammended.pdf
NIST Federal Information Processing Standards (FIPS PUB 197) Advanced Encryption Standard (November 2001), http://www.nist.gov/aes
CAST, Advanced Encryption Standard Core, http://www.cast-inc.com/cores/aes/index.shtml
Elbirt, A., Yip, W., Chetwynd, B., Paar, C.: An FPGAbased performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Trans. of VLSI Systems 9(4), 545–557 (2001)
ThongKhome, K., Thanavijitpun, C.: FPGA Design of AES C Architecture for Portable Hard Disk
Kim, C.H.: Improved Differential Fault Analysis on AES Key Schedule
Wong, M.M., Wong, M.L.D.: A High Throughput Low Power Compact AES S-box Implementation using Composite Field Arithmetic and Algebraic Normal Form Representation
Rijmen, V.: Efficient implementation S-box, http://ftp.comms.scitech.susx.ac.uk/fft/crypto/rijndaelsbox.pdf
Jutla, C., Kumar, V., Rudra, A.: On the Complexity of Isomorphic Galois Field Transforms. IBM Research Report, vol. RC22652, W0211–W0243 (November 2002)
Chantarawong, S., Noo-intara, P., Choomchuay, S.: An Architecture for S-Box Computation in the AES. In: Proc. of Information and Computer Engineering Workshop 2004 (ICEP 2004), pp. 157–162 (2004)
Hodjat, A., Verbauwhede, I.: Minimum Area Cost for a 30 to 70 Gbits/s AES Processor
Jing, M.-H., Chen, J.-H., Chen, Z.-H.: Diversified MixColumn Transformation of AES
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© 2013 Springer India
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Bellikatti, V.I., Chetan, S., Shivaputra, Kushal, K.S. (2013). Design of High Security and Performance System for Storage Devices Using AES. In: Kumar M., A., R., S., Kumar, T. (eds) Proceedings of International Conference on Advances in Computing. Advances in Intelligent Systems and Computing, vol 174. Springer, New Delhi. https://doi.org/10.1007/978-81-322-0740-5_42
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DOI: https://doi.org/10.1007/978-81-322-0740-5_42
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-0739-9
Online ISBN: 978-81-322-0740-5
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