System Verilog Based SOC Verification Environment for FLASH MEMORY

Abstract

This paper discusses a generic flow on how an automated SV-based test bench environment which is randomized with constraints can verify a SOC effectively for its functionality and code coverage [1]. Today, in the era of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification [1] consumes about 70 % of the design effort. Automation lets you do something else while a machine completes a task autonomously, faster and with predictable results. Automation requires standard processes with well-defined inputs and outputs. Not all processes can be automated. Because of the variety of functions, interfaces, protocols, and transformations that must be verified, it is not possible to provide a general purpose automation solution for verification, given today’s technology. It is possible to automate some portion of the verification process, especially when applied to a narrow application domain. Tools automating various portions of the verification process are being introduced. Here, we have a SOC with a ARM multicore processor which talks to one of the peripherals, which is a flash memory (CODE FLASH and a DATA FLASH). The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence OVM libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the methodology [2] implemented in system verilog for SOC verification.