Abstract
We review surface-potential-based approach to compact modeling of bulk MOS transistors and provide introduction to the widely used PSP model jointly developed by the Arizona State University and NXP Semiconductors. The emphasis is on the interplay between the mathematical structure of the compact model and its capabilities for the circuit design applications.
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Acknowledgments
This work is supported in part by the Semiconductor Research Corporation and by the Compact Model Council (CMC). The detailed evaluation by the CMC members of several versions of the PSP model is deeply appreciated. The authors are much indebted to Dr. C.C. McAndrew for the numerous discussions of the material presented in this chapter. We are grateful to Dr. J. Watts for the test data shown in Fig. 1.14 and to G. Dessai for reading the manuscript and numerous useful comments.
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Gildenblat, G. et al. (2010). Surface-Potential-Based Compact Model of Bulk MOSFET. In: Gildenblat, G. (eds) Compact Modeling. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8614-3_1
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