Skip to main content
SpringerLink
Log in

Program and erase of NAND memory arrays

  • Chapter
  • First Online:
Inside NAND Flash Memories

Abstract

The purpose of NAND Flash memories as a non-volatile memory is to store the user data for years without requiring a supply voltage. The state of the art memory cell for this purpose in NAND Flash is the 1T floating gate memory cell, which is based on a MOSFET. In contrast to the 1T1C DRAM cell, which consists of an access transistor and a separate capacitance as charge storage node, the 1T floating gate cell is a MOSFET whose gate dielectric is split with a charge storage node in between. This charge storing node, usually made of poly-silicon, is electrically isolated completely by the surrounding dielectrics. Its stored charges represent the information, and may be altered according to the user data by the program operation.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 189.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 249.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. D. Kahng and S. Sze, “A floating-gate and its application to memory devices,” The Bell System Technical Journal, vol. 46, no. 4, pp. 1288–1295, 1967.

    Google Scholar 

  2. J. Yeargain and C. Kuo, “A high density floating-gate EEPROM cell,” in International Electron Devices Meeting, 1981. IEDM’81,, vol. 27, 1981, pp. 24–27, 1981.

    Google Scholar 

  3. G. Ginami et al., “Survey on Flash technology with specific attention to the critical process parameters related to manufacturing,” Proceedings of the IEEE, vol. 91, no. 4, pp. 503–522, April 2003.

    Article  Google Scholar 

  4. S. Aritome et al., “A 0.67 µm2 self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs,” in International Electron Devices Meeting, 1994. IEDM ’94. Technical Digest., pp. 61–64, Dec 1994.

    Google Scholar 

  5. W. Johnson et al., “A 16Kb electrically erasable nonvolatile memory,” in Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International, vol. XXIII, pp. 152–153, Feb. 1980.

    Google Scholar 

  6. B. Govoreanu, D. Brunco, and J. V. Houdt, “Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities,” Solid-State Electronics, vol. 49, no. 11, pp. 1841–1848, Nov 2005.

    Article  Google Scholar 

  7. K. Gibb and H. Gu. (2008, 11) High-k Gate Dielectrics - the Future Is Friendly for NAND Flash. Chipworks. [Online]. Available: http://www.chipworks.com/blogs/

    Google Scholar 

  8. K. K. Likharev, “Layered tunnel barriers for nonvolatile memory devices,” Applied Physics Letters, vol. 73, no. 15, pp. 2137–2139, 1998. [Online]. Available: http://link.aip.org/link/?APL/73/2137/1

    Article  Google Scholar 

  9. M. Specht, M. Städele, and F. Hofmann, “Simulation of High-K Tunnel Barriers for Nonvolatile Floating Gate Memories,” in Proceeding of the 32nd European Solid-State Device Research Conference, Sept. 24–26, 2002, pp. 599–602.

    Google Scholar 

  10. N. Chan et al., “Metal control gate for sub-30nm floating gate NAND memory,” in Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual, pp. 1–4, Nov. 2008.

    Google Scholar 

  11. S. Mori et al., “ONO inter-poly dielectric scaling for nonvolatile memory applications,” IEEE Transactions on Electron Devices, vol. 38, no. 2, pp. 386–391, Feb 1991.

    Article  Google Scholar 

  12. B. Govoreanu et al., “Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention,” in International Electron Devices Meeting, 2006. IEDM ’06, pp. 1–4, Dec. 2006.

    Google Scholar 

  13. S. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. Wiley, Inc., Hoboken, NJ, 2007.

    Google Scholar 

  14. R. H. Fowler and L. Nordheim, “Electron emission in intense electric fields,” Proceedings of the Royal Society of London, vol. 119, no. 781, pp. 173–181, May 1928.

    Article  MATH  Google Scholar 

  15. M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO,” Journal of Applied Physics, vol. 40, no. 1, pp. 278–283, 1969. [Online]. Available: http://link.aip.org/link/?JAP/40/278/1

    Article  Google Scholar 

  16. J. Sune, P. Olivo, and B. Ricco, “Quantum-mechanical modeling of accumulation layers in MOS structure,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1732–1739, July 1992.

    Article  Google Scholar 

  17. T. Tanaka et al., “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” Symposium on VLSI Circuits, 1990. Digest of Technical Papers, pp. 105–106, June 1990.

    Google Scholar 

  18. K.-D. Suh et al., “A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme,” Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International, pp. 128–129, 350, Feb 1995.

    Google Scholar 

  19. P. Apte and K. Saraswat, “Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown,”IEEE Transactions on Electron Devices, vol. 41, no. 9, pp. 1595–1602, Sept 1994.

    Article  Google Scholar 

  20. M. F. Beug, N. Chan, T. Hoehr, L. Mueller-Meskamp, and M. Specht, “Investigation of program saturation in scaled interpoly dielectric floating-gate memory devices,” IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1698–1704, Aug. 2009.

    Article  Google Scholar 

  21. T. Tanaka et al., “A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND Flash memory,” IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1366–1373, Nov 1994.

    Article  Google Scholar 

  22. K. Takeuchi et al., “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput,” Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, pp. 507–516, Feb. 2006.

    Google Scholar 

  23. K.-D. Suh et al., “A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme,” IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1149–1156, Nov. 1995.

    Article  Google Scholar 

  24. S. Satoh et al., “A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance,” International Electron Devices Meeting, 1997. IEDM ’97. Technical Digest., pp. 291–294, Dec 1997.

    Google Scholar 

  25. S. Satoh et al., “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND Flash memories,” in VLSI Technology, 1998. Symposium on Digest of Technical Papers, pp. 108–109, June 1998.

    Google Scholar 

  26. C. Friederich, M. Specht, T. Lutz, F. Hofmann, L. Dreeskornfeld, W. Weber, J. Kretz, T. Melde, W. Rösner, E. Landgraf, J. Hartwich, M. Stadele, L. Risch, and D. Richter, “Multi-level p+ tri-gate SONOS NAND string arrays,” IEDM’ 06. International Electron Devices Meeting Technical Digest, pp. 1–4, Dec. 2006.

    Google Scholar 

  27. H. Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in IEEE Symposium on VLSI Technology, June 2007, pp. 14–15.

    Google Scholar 

  28. Y. Komori et al., “Disturbless Flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device,” in IEEE International Electron Devices Meeting (IEDM’ 08), pp. 1–4, Dec. 2008.

    Google Scholar 

  29. J.-D. Lee et al., “A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current,” Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st, pp. 31–33, 2006.

    Google Scholar 

  30. K.-T. Park et al., “Scalable Wordline Shielding Scheme using Dummy Cell beyond 40 nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell,” Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2188–2192, 2007. [Online]. Available: http://jjap.ipap.jp/link?JJAP/46/2188/

    Article  Google Scholar 

  31. T. Cho et al., “A dual-mode NAND Flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes,” IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1700–1706, Nov. 2001.

    Article  Google Scholar 

  32. J. Lee et al., “A 1.8 V 2 Gb NAND Flash memory for mass storage applications,” IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers, ISSCC, pp. 290–494, vol.1, 2003.

    Google Scholar 

  33. J. Lee et al., “A 90-nm CMOS 1.8-V 2-Gb NAND Flash memory for mass storage applications,” IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1934–1942, Nov. 2003.

    Article  Google Scholar 

  34. T.-S. Jung et al., “A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND Flash memory technology,” IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1748–1757, Nov. 1997.

    Article  Google Scholar 

  35. K. Takeuchi, S. Satoh, K. Imamiya, and K. Sakui, “A source-line programming scheme for low-voltage operation NAND Flash memories,” IEEE Journal of Solid-State Circuits, vol. 35, no. 5, pp. 672–681, May 2000.

    Article  Google Scholar 

  36. T.-S. Jung et al., “A 3.3 V 128 Mb multi-level NAND Flash memory for mass storage applications,” Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International, pp. 32–33, 412, Feb 1996.

    Google Scholar 

  37. T.-S. Jung et al., “A 117-mm2 3.3-V only 128-Mb multilevel NAND Flash memory for mass storage applications,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1575–1583, Nov. 1996.

    Article  Google Scholar 

  38. S. Hur et al., “Effective program inhibition beyond 90 nm NAND Flash memories,” in Proceedings of IEEE 20th Non-Volatile Semiconductor Memory Workshop, pp. 44–45, 2004.

    Google Scholar 

  39. D. Oh et al., “A New Self-Boosting Phenomenon by Soure/Drain Depletion Cut-off in NAND Flash Memory,” in Proceedings of 22nd IEEE Non-Volatile Semiconductor Memory Workshop, pp. 39–41, Aug. 2007.

    Google Scholar 

  40. J.-y. Jeong, J.-s. Yeom, and S.-s. Lee, “Method of programming non-volatile semiconductor memory device,” Patent 20 020 118 569, August, 2002. [Online]. Available: http://www.freepatentsonline.com/y2002/0118569.html

  41. J. W. Lutze, J. Chen, Y. Li, and M. Higashitani, “Source side self boosting technique for non-volatile memory,” Patent 6 859 397, February, 2005. [Online]. Available: http://www.freepatentsonline.com/6859397.html

  42. J.-K. Kim, H.-B. Pyeon, H. Oh, R. Schuetz, and P. Gillingham, “Low Stress Program and Single Wordline Erase Schemes for NAND Flash Memory,” in Proceedings of 22nd IEEE Non-Volatile Semiconductor Memory Workshop, pp. 19–20, Aug. 2007.

    Google Scholar 

  43. K.-T. Park, M. Kang, S. Hwang, Y. Song, J. Lee, H. Joo, H.-S. Oh, J.-h. Kim, Y.-t. Lee, C. Kim, and W. Lee, “Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND Flash memories,” in Symposium on VLSI Circuits, pp. 24–25, June 2009.

    Google Scholar 

  44. D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical modeling of reliability and scaling projections for Flash memories,” in International Electron Devices Meeting, 2001. IEDM Technical Digest, pp. 32.2.1–32.2.4, 2001.

    Google Scholar 

  45. L. Larcher, “Statistical simulation of leakage currents in MOS and Flash memory devices with a new multiphonon trap-assisted tunneling model,” IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1246–1253, May 2003.

    Article  Google Scholar 

  46. L.-C. Hu, A.-C. Kang, J. Shih, Y.-F. Lin, K. Wu, and Y.-C. King, “Statistical modeling for postcycling data retention of split-gate Flash memories,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 1, pp. 60–66, March 2006.

    Article  Google Scholar 

  47. H. Kurata et al., “The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories,” Symposium on VLSI Circuits, 2006. Digest of Technical Papers, pp. 112–113, 2006.

    Google Scholar 

  48. N. Tega et al., “Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory,” in International Electron Devices Meeting, 2006. IEDM ’06, pp. 1–4, Dec. 2006.

    Chapter  Google Scholar 

  49. C. M. Compagnoni et al., “Statistical Model for Random Telegraph Noise in Flash Memories,” IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 388–395, Jan. 2008.

    Article  MathSciNet  Google Scholar 

  50. M. Momodomi et al., “A 4 Mb NAND EEPROM with tight programmed Vt distribution,” IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 492–496, Apr 1991.

    Article  Google Scholar 

  51. J. Chen and Y. Fong, “High density non-volatile Flash memory without adverse effects of electric field coupling between adjacent floating gates,” US Patent 5 867 429, February, 1999. [Online]. Available: http://www.freepatentsonline.com/5867429.html

  52. J.-D. Lee, S.-H. Hur, and J.-D. Choi, “Effects of floating-gate interference on NAND Flash memory cell operation,” IEE Electron Device Letters, vol. 23, no. 5, pp. 264–266, May 2002.

    Article  Google Scholar 

  53. A. Ghetti, L. Bortesi, and L. Vendrame, “3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories,” Solid-State Electronics, vol. 49, no. 11, pp. 1805–1812, 2005.

    Article  Google Scholar 

  54. K. Kim, “Technology for sub-50nm DRAM and NAND Flash manufacturing,” in IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest, pp. 323–326, Dec. 2005.

    Chapter  Google Scholar 

  55. D. Kang et al., “Improving the Cell Characteristics Using Low-k Gate Spacer in 1Gb NAND Flash Memory,” in International Electron Devices Meeting, 2006. IEDM ’06, pp. 1–4, Dec. 2006.

    Chapter  Google Scholar 

  56. K.-T. Park, “A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond,” IEEE Symposium on VLSI Circuits, pp. 188–189, June 2007.

    Google Scholar 

  57. N. Shibata et al., “A 70nm 16Gb 16-level-cell NAND Flash Memory,” IEEE Symposium on VLSI Circuits,pp. 190–191, June 2007.

    Google Scholar 

  58. K. Yano et al., “Single-electron memory for giga-to-tera bit storage,” Proceedings of the IEEE, vol. 87, no. 4, pp. 633–651, Apr. 1999.

    Article  Google Scholar 

  59. G. Molas et al., “Impact of few electron phenomena on floating-gate memory reliability,” in IEEE International Electron Devices Meeting, 2004. IEDM Technical Digest, pp. 877–880, Dec. 2004.

    Chapter  Google Scholar 

  60. G. Molas et al., “Degradation of floating-gate memory reliability by few electron phenomena,” IEEE Transactions on Electron Devices, vol. 53, no. 10, pp. 2610–2619, Oct. 2006.

    Article  Google Scholar 

  61. C. Compagnoni et al., “First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming,” in IEEE International Electron Devices Meeting, 2007. IEDM ‘07, pp. 165–168, Dec. 2007.

    Chapter  Google Scholar 

  62. C. Compagnoni et al., “Analytical model for the electron-injection statistics during programming of nanoscale NAND Flash memories,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3192–3199, Nov. 2008.

    Article  Google Scholar 

  63. C. Friederich, J. Hayek, A. Kux, T. Müller, N. Chan, G. Köbernik, M. Specht, D. Richter, and D. Schmitt-Landsiedel, “Novel model for cell - system interaction (MCSI) in NAND Flash,” in International Electron Devices Meeting, Technical Digest. IEDM 08, Dec. 2008.

    Google Scholar 

  64. V. Sobolev, Encyclopaedia of Mathematics. Springer, 2002, ch. Convolution of functions.

    Google Scholar 

  65. J. Van Houdt, “High-k materials for nonvolatile memory applications,” in Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International, pp. 234–239, 17–21, 2005.

    Google Scholar 

  66. K. Takeuchi, T. Tanaka, and T. Tanzawa, “A Multi-page Cell Architecture for High-speed Programming Multi-level NAND Flash Memories,” VLSI Circuits, 1997. Symposium on Digest of Technical Papers, pp. 67–68, June 1997.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute for Technical Electronics, Technische Universität München, München, Germany

    Christoph Friederich

Authors
  1. Christoph Friederich
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Christoph Friederich .

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Friederich, C. (2010). Program and erase of NAND memory arrays. In: Inside NAND Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9431-5_3

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-9431-5_3

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-9430-8

  • Online ISBN: 978-90-481-9431-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation