A Functional-Segmentation DAC Design Using Harmonic Distortion Suppression Method

Abstract

This chapter presents a validation in practice for the new DAC correction method for suppression of HD, which is presented in Chap. 13. An 180 nm CMOS test-chip implementation and a measurements setup are presented. The test-chip design uses functional unary segmentation of four 12 bit sub-DACs. Measurement results are reported for two different implementations of the method. The first implementation uses a single 12 bit conventional DAC to emulate two virtual sub-DACs, converting π/3 phase-shifted signals. Measurement results show more than 10 dB improvement of the DAC linearity. The second implementation of the method uses two real 12 bit sub-DACs, converting π/3 phase-shifted signals. Measurement results show SFDR = 80 dB for f_in = 16.9 MHz. For OFDM-like multi-tone measurements, the measured improvement of the DAC linearity is about 8 dB.