Layout and Verification

Abstract

Once the circuit design is finished, we begin the layout design. You’re given a thick layout manual and casually told, “Next up for you is layout.” A large amount of creativity is not necessary, but rather a persistent and tenacious effort is required, and within the design cycle, this step is “painful” and takes the most time. In turn, it is no exaggeration to say that this step determines whether the created chip will function successfully or not. This chapter starts with three-dimensional transistor structures and layer-by-layer LSI fabrication process to understand the relationship between the detailed transistor structure and each layer of the circuit layout. There are many kinds of design rules we must follow to have the fabricated chip operate as being designed, and this chapter explains the background of the rules including basic rules such as minimum width and spacing, as well as grid, density rules, dummy metal, dummy transistors, and antenna rules. Then typical layout examples of NMOS, PMOS, resistors, capacitors, and inductors are shown with some layout techniques. Also principles of the typical layout verifications of DRC, LVS, ERC, antenna, and density check are also explained.